US5644742A — Processor structure and method for a time-out che…

Claim 1

Independent Claim 122 words

In a central processing unit (CPU) having an instruction issue means, instruction execution means, and a data store for storing data, a method for bounding exception handling for exceptions occurring in said execution means; said method comprising the steps of: establishing a predetermined threshold for the number of occurrences of a specified event that defines a time-out condition and storing said threshold in a first data store within said CPU; counting occurrences of a said specified event in a counter within said CPU and storing said number of occurrences as a count in a second data store within said CPU; comparing said count with said threshold; forming a time-out checkpoint when said count is equal to or greater than said time-out condition.

Claim 2

Dependent Claim 122 words

In a central processing unit (CPU) having an instruction issue means, instruction execution means, and a data store for storing data, a method for bounding exception handling for exceptions occurring in said execution means; said method comprising the steps of: establishing a predetermined threshold for the number of occurrences of a specified event that defines a time-out condition and storing said threshold in a first data store within said CPU; counting occurrences of a said specified event in a counter within said CPU and storing said number of occurrences as a count in a second data store within said CPU; comparing said count with said threshold; forming a time-out checkpoint when said count is equal to or greater than said time-out condition.

Claim 3

Dependent Claim 46 words

The method in claim 1, further comprising the steps of: initializing said count to an initial value prior to execution of a first instruction; and resetting said count to said initial state after a checkpoint has been formed including after said time-out checkpoint has been formed.

Claim 4

Dependent Claim 42 words

The method in claim 2, wherein said specified event is issuance of any instruction by said central processing unit so that formation of said time-out checkpoint limits the number of instructions issued between successively formed checkpoints to said predetermined number of instructions.

Claim 5

Dependent Claim 12 words

The method in claim 3, wherein said instruction has arbitrary instruction attributes.

Claim 6

Dependent Claim 19 words

The method in claim 2, wherein said specified event is execution of a predetermined number of machine clock cycles.

Claim 7

Dependent Claim 23 words

The method in claim 2, wherein said specified event is the number of instruction issue cycles that have passed without forming a checkpoint.

Claim 8

Dependent Claim 33 words

The method in claim 3, wherein said step of forming said timeout checkpoint comprises storing state information characterizing complete state of said CPU including storing state information for all registers in said CPU.

Claim 9

Dependent Claim 45 words

The method in claim 3, wherein said step of forming said timeout checkpoint comprises storing state information characterizing the state of a register rename map storing only indicia of data changed since the last checkpoint, including the last time-out checkpoint, was formed within said CPU.

Claim 10

Dependent Claim 17 words

The method in claim 8, wherein said indicia comprises a mapping of logical registers to physical registers.

Claim 11

Dependent Claim 62 words

The method in claim 3, further comprising the step of recovering from an execution error caused by a faulting instruction including the steps of: restoring earlier processor state from a checkpoint formed for a checkpointed instruction sequentially before said faulting instruction; backing up said CPU from said faulting instruction to said earlier checkpointed instruction; and re-executing instructions forward from said checkpointed instruction.

Claim 12

Dependent Claim 94 words

The method in claim 3, further comprising the step of recovering from an execution error caused by a faulting instruction including the steps of: restoring earlier processor state from a checkpoint formed for a checkpointed instruction sequentially later than said faulting instruction; backing up said CPU from said faulting instruction to said sequentially later checkpointed instruction; backstepping said CPU to said faulting instruction including restoring processor state for each instruction lying sequentially between said later checkpointed instruction and said faulting instruction in a backward step-by-step manner; and re-executing instructions forward from said faulting instruction.

Claim 13

Dependent Claim 52 words

The method in claim 3, further comprising the steps of: if all checkpoints are allocated at the time a timeout checkpoint becomes due, delaying formation of the timeout checkpoint according to predetermined rules rather than stalling the machine as might be required to maintain precise state for an instruction decode type checkpoint.

Claim 14

Dependent Claim 22 words

The method in claim 12, wherein the predetermined rules comprise delaying formation of the timeout checkpoint for a predetermined number of cycles.

Claim 15

Independent Claim 321 words

A method for bounding exception handling in a central processing unit (CPU) having an instruction issue unit for issuing instructions, said method comprising the steps of: establishing a predetermined time-out threshold count in a data store within said CPU; storing an initial count number in a data store within said CPU; sending an instruction issued signal from said instruction issue unit during a CPU clock cycle in which an instruction was issued to indicate that at least one instruction was issued during said CPU clock cycle; providing a time-out counter, responsive to said instruction issued signal, for counting the number of said instruction issued signals received; receiving said instruction issued signals; counting the number of instruction issued signals received during each CPU clock cycle and adding the number to the accumulated number stored in a data store within said CPU; resetting said count number to an initial value whenever a checkpoint is formed, including a checkpoint formed in response to a make time-out checkpoint signal and a checkpoint formed in response to decoded instruction attributes; during each CPU clock cycle, comparing said accumulated count number with said time-out threshold count to determine if said accumulated count number is greater than or equal to said threshold count; generating, within said timeout-counter, a make time-out checkpoint signal when said accumulated count number is greater than or equal to said threshold count; communicating said make time-out checkpoint signal to said instruction issue unit informing said issue unit that a checkpoint timeout condition has occurred, and that a checkpoint should be formed; forming a checkpoint in response to said make time-out checkpoint signal and resetting said count number to said initial value; whereby formation of said time-out checkpoint limits the number of instructions issued between successively formed checkpoints to a predetermined number of instructions and thereby bounds the number of issued instructions that may have to be undone and re-executed when an exception condition occurs.

Claim 16

Independent Claim 321 words

A method for bounding exception handling in a central processing unit (CPU) having an instruction issue unit for issuing instructions, said method comprising the steps of: establishing a predetermined time-out threshold count in a data store within said CPU; storing an initial count number in a data store within said CPU; sending an instruction issued signal from said instruction issue unit during a CPU clock cycle in which an instruction was issued to indicate that at least one instruction was issued during said CPU clock cycle; providing a time-out counter, responsive to said instruction issued signal, for counting the number of said instruction issued signals received; receiving said instruction issued signals; counting the number of instruction issued signals received during each CPU clock cycle and adding the number to the accumulated number stored in a data store within said CPU; resetting said count number to an initial value whenever a checkpoint is formed, including a checkpoint formed in response to a make time-out checkpoint signal and a checkpoint formed in response to decoded instruction attributes; during each CPU clock cycle, comparing said accumulated count number with said time-out threshold count to determine if said accumulated count number is greater than or equal to said threshold count; generating, within said timeout-counter, a make time-out checkpoint signal when said accumulated count number is greater than or equal to said threshold count; communicating said make time-out checkpoint signal to said instruction issue unit informing said issue unit that a checkpoint timeout condition has occurred, and that a checkpoint should be formed; forming a checkpoint in response to said make time-out checkpoint signal and resetting said count number to said initial value; whereby formation of said time-out checkpoint limits the number of instructions issued between successively formed checkpoints to a predetermined number of instructions and thereby bounds the number of issued instructions that may have to be undone and re-executed when an exception condition occurs.

Claim 17

Dependent Claim 95 words

The method in claim 14, further comprising the steps, after said step of comparing said accumulated count number with said time-out threshold count and before said step of generating, of: determining if an instruction in the instruction issue window due to be issued in the same CPU clock cycle requires a checkpoint based on instruction attributes, delaying generation of said make time-out checkpoint signal, forming a checkpoint in response to said decoded instruction; and resetting said accumulated count number to said initial value checkpoint in response to checkpoint formation for instruction attribute based checkpoint formation.

Claim 18

Dependent Claim 132 words

In a processor having an instruction issue unit generating an instruction issued signal upon issue of an instruction, a checkpoint formation unit generating a checkpoint formed signal upon formation of a checkpoint storing processor state prior to execution of said instruction, a timeout checkpoint counter apparatus comprising: a counter circuit having an enable input port for receiving said instruction issued signal and incrementing a count in response to each received instruction issued signal, a reset port for receiving said checkpoint formed signal, and an accumulated count output signal; a data store for storing a predetermined time-out threshold count; and a comparator for comparing said stored time-out threshold count with said accumulated count output signal; said counter circuit outputting a timeout checkpoint request signal after counting a predetermined number of instruction issued signals.

Claim 19

Dependent Claim 132 words

In a processor having an instruction issue unit generating an instruction issued signal upon issue of an instruction, a checkpoint formation unit generating a checkpoint formed signal upon formation of a checkpoint storing processor state prior to execution of said instruction, a timeout checkpoint counter apparatus comprising: a counter circuit having an enable input port for receiving said instruction issued signal and incrementing a count in response to each received instruction issued signal, a reset port for receiving said checkpoint formed signal, and an accumulated count output signal; a data store for storing a predetermined time-out threshold count; and a comparator for comparing said stored time-out threshold count with said accumulated count output signal; said counter circuit outputting a timeout checkpoint request signal after counting a predetermined number of instruction issued signals.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2000-06-30	2000-12-30	2001-07-01	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2004-06-30	2004-12-30	2005-07-01	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2008-06-30	2008-12-30	2009-07-01	$7700.00	Window Closed / Lapsed

Processor structure and method for a time-out checkpoint

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