Apparatus for executing a RISC store and RI instruction pair in two clock cycles

Claim 2

In a reduced instruction set computer (RISC) system comprising a first instruction having three read addresses and a second instruction having a read address, a data constant, and a write address, a central processing unit (CPU) for executing said first and second instruction in two clock cycles, said CPU comprising: (a) first register means coupled to an instruction issuing unit of said RISC system for receiving said first and second instructions in a first and a second clock cycle as inputs, and in response, storing the first and second read addresses of said first instruction during said first clock cycle, said read address, data constant and write address of said second instruction during said second clock cycle, and the third read address of said first instruction during said first and second clock cycles, and outputting the first and second read addresses of said first instruction during said first clock cycle, the third read address of said first instruction and said read address, data constant, and write address of said second instruction during said second clock cycle; (b) second register means coupled to said first register means for receiving the first and second read addresses of said first instruction during said first clock cycle, the third read address of said first instruction and said read address, data constant, and write address of said second instruction during said second clock cycle, and in response, outputting a first and a second data output during said first clock cycle, and a third and a fourth data output during said second clock cycle, and storing a data input during said second clock cycle; (c) address generation means coupled to said second register means and a memory unit of said RISC system for receiving said first and second data output during said first clock cycle, and in response, generating a memory address for said memory unit during said first clock cycle; (d) arithmetic means coupled to said first and second register means for receiving said fourth data output and data constant during said second clock cycle, and in response, generating said data input for said second register means during said second clock cycle, said third data output being received by said memory unit during said second clock cycle.

Claim 3

The CPU as set forth in claim 1, wherein, said first register means comprises: (a.1) an instruction register coupled to said instruction issuing unit, said second register means, and said arithmetic means for receiving and storing said first and second instructions during said first and second clock cycles, outputting for said second register means said first and second read addresses of said first instruction during said first clock cycle, and said read and write addresses of said second instruction during said second clock cycle, outputting for said arithmetic means said data constant of said second instruction during said second clock cycle, and outputting said third read address of said first instruction when transitioning from said first clock cycle to said second clock cycle; (a.2) a carryover register coupled to said instruction register for receiving said third read address of said first instruction when transitioning from said first clock cycle to said second clock cycle, storing and outputting said third read address of said first instruction during said second clock cycle; and (a.3) a multiplexor coupled to said instruction register and said carryover register for selecting said carryover register, and outputting for said second register means said third read address of said first instruction during said second clock cycle.

Claim 4

The CPU as set forth in claim 1, wherein, said RISC system further comprises a third instruction having at least two read addresses, and said third instruction is issued by said instruction issuing unit in lieu of said second instruction during said second clock cycle, said first register means, during said second clock cycle, receiving said third instruction in lieu of said second instruction, storing said at least two read addresses of said third instruction in lieu of said read address, data constant, and write address of said second instruction, and outputting a notification signal indicating to said instruction issuing unit the necessity of reissuing said third instruction in lieu of said read address, data constant, and write address of said second instruction; said second register means, during said second clock cycle, receiving only said third read address of said first instruction, outputting only said third data output, and storing no data input; and said arithmetic means, during said second clock cycle, performing no operation.

Claim 5

A reduced instruction set computer (RISC) system comprising: (a) instruction issuing means for issuing a first instruction having three read addresses and a second instruction having a read address, a data constant, and a write address; (b) a central processing unit (CPU) for executing said first and second instruction in two clock cycles, said CPU comprising (b.1) first register means coupled to said instruction issuing means for receiving said first and second instructions in a first and a second clock cycle as inputs, and in response, storing the first and second read addresses of said first instruction during said first clock cycle, said read address, data constant and write address of said second instruction during said second clock cycle, and the third read address of said first instruction during said first and second clock cycles, and outputting the first and second read addresses of said first instruction during said first clock cycle, the third read address of said first instruction and said read address, data constant, and write address of said second instruction during said second clock cycle; (b.2) second register means coupled to said first register means for receiving the first and second read addresses of said first instruction during said first clock cycle, the third read address of said first instruction and said read address, data constant, and write address of said second instruction during said second clock cycle, and in response, outputting a first and a second data output during said first clock cycle, and a third and a fourth data output during said second clock cycle, and storing a data input during said second clock cycle; (b.3) address generation means coupled to said second register means for receiving said first and second data output during said first clock cycle, and in response, generating a memory address during said first clock cycle; (b.4) arithmetic means coupled to said first and second register means for receiving said fourth data output and data constant during said second clock cycle, and in response, generating said data input for said second register means during said second clock cycle; (c) memory means coupled to said address generation means and said second register means for receiving said memory address during said first clock cycle, receiving and storing said third data output in accordance to said previously received memory address during said second clock cycle.

Claim 6

A reduced instruction set computer (RISC) system comprising: (a) instruction issuing means for issuing a first instruction having three read addresses and a second instruction having a read address, a data constant, and a write address; (b) a central processing unit (CPU) for executing said first and second instruction in two clock cycles, said CPU comprising (b.1) first register means coupled to said instruction issuing means for receiving said first and second instructions in a first and a second clock cycle as inputs, and in response, storing the first and second read addresses of said first instruction during said first clock cycle, said read address, data constant and write address of said second instruction during said second clock cycle, and the third read address of said first instruction during said first and second clock cycles, and outputting the first and second read addresses of said first instruction during said first clock cycle, the third read address of said first instruction and said read address, data constant, and write address of said second instruction during said second clock cycle; (b.2) second register means coupled to said first register means for receiving the first and second read addresses of said first instruction during said first clock cycle, the third read address of said first instruction and said read address, data constant, and write address of said second instruction during said second clock cycle, and in response, outputting a first and a second data output during said first clock cycle, and a third and a fourth data output during said second clock cycle, and storing a data input during said second clock cycle; (b.3) address generation means coupled to said second register means for receiving said first and second data output during said first clock cycle, and in response, generating a memory address during said first clock cycle; (b.4) arithmetic means coupled to said first and second register means for receiving said fourth data output and data constant during said second clock cycle, and in response, generating said data input for said second register means during said second clock cycle; (c) memory means coupled to said address generation means and said second register means for receiving said memory address during said first clock cycle, receiving and storing said third data output in accordance to said previously received memory address during said second clock cycle.

Claim 7

The RISC system as set forth in claim 4, wherein, said first register means comprises: (b.1.1) an instruction register coupled to said instruction issuing means, said second register means, and said arithmetic means for receiving and storing said first and second instructions during said first and second clock cycles, outputting for said second register means said first and second read addresses of said first instruction during said first clock cycle, and said read and write addresses of said second instruction during said second clock cycle, outputting for said arithmetic means said data constant of said second instruction during said second clock cycle, and outputting said third read address of said first instruction when transitioning from said first clock cycle to said second clock cycle; (b.1.2) a carryover register coupled to said instruction register for receiving said third read address of said first instruction when transitioning from said first clock cycle to said second clock cycle, storing and outputting said third read address of said first instruction during said second clock cycle; and (b.1.3) a multiplexor coupled to said instruction register and said carryover register for selecting said carryover register, and outputting for said second register means said third read address of said first instruction during said second clock cycle.

Claim 8

The RISC system as set forth in claim 4, wherein, said instruction issuing means, during said second clock cycle, issues a third instruction having at least two read addresses in lieu of said second instruction; said first register means, during said second clock cycle, receiving said third instruction in lieu of said second instruction, storing said at least two read addresses of said third instruction in lieu of said read address, data constant, and write address of said second instruction, and outputting a notification signal indicating to said instruction issuing means the necessity of reissuing said third instruction in lieu of said read address, data constant, and write address of said second instruction; said second register means, during said second clock cycle, receiving only said third read address of said first instruction, outputting only said third data output, and storing no data input; and said arithmetic means, during said second clock cycle, performing no operation.