Semiconductor dynamic random access memory device variable in refresh cycle

Claim 2

A semiconductor memory device fabricated on a semiconductor chip comprising: a memory cell array; a plurality of first terminal means for communicating an address signal and a data signal through an external device; an access means connected to said plurality of first terminal means, and responsive to said address signal for selecting at least one memory cell from said memory cell array in a memory access mode, thereby carrying out a read-out of a data represented by said data signal and a write-in of a data represented by said data signal on the selected memory cell; a second terminal means selected from said plurality of first terminal means, and receiving information for determining a refresh cycle from the outside of said semiconductor chip in said refresh mode; and a refresh means including a refresh timer for periodically generating a timer signal, and carrying out a refreshing operation on said memory cell array on the basis of said timer signal supplied from said refresh timer in a refresh mode, said refresh means further including a means responsive to said information so as to cause said refresh timer to change an interval of said timer signal.

Claim 3

A semiconductor dynamic random access memory device having a memory access mode for a read-out of data and a write-in of data and a refresh mode for refreshing data, comprising: a memory cell array having a plurality of addressable memory cells for storing said data, respectively; an addressing system responsive to an external address signal for making said plurality of memory cells selectively accessible in said memory access mode, and responsive to a refresh address signal for selectively reading out said data from said plurality of memory cells in said refresh mode; a sense amplifier unit coupled to said memory cell array for magnifying potential differences indicative of said data in both of said memory access mode and said refresh mode; a plurality of first terminal means receiving said external address signal and a first data signal and outputting a second data signal for communicating with an external device; a self-refreshing system including a second terminal means selected from said plurality of first terminal means for receiving a control data signal indicative of a time interval of said refresh cycle in said refresh mode, a refresh cycle regulating means coupled to said second terminal means for receiving said control data signal and producing a control data signal indicative of time intervals corresponding to said time interval represented by said control data signal, a timer means responsive to said control data signal for periodically producing a timing control signal at said time intervals in said refresh mode, and a refresh address generating means responsive to said timing control signal for periodically incrementing an address represented by said refresh address signal in said refresh mode.

Claim 4

A semiconductor dynamic random access memory device having a memory access mode for a read-out of data and a write-in of data and a refresh mode for refreshing data, comprising: a memory cell array having a plurality of addressable memory cells for storing said data, respectively; an addressing system responsive to an external address signal for making said plurality of memory cells selectively accessible in said memory access mode, and responsive to a refresh address signal for selectively reading out said data from said plurality of memory cells in said refresh mode; a sense amplifier unit coupled to said memory cell array for magnifying potential differences indicative of said data in both of said memory access mode and said refresh mode; a plurality of first terminal means receiving said external address signal and a first data signal and outputting a second data signal for communicating with an external device; a self-refreshing system including a second terminal means selected from said plurality of first terminal means for receiving a control data signal indicative of a time interval of said refresh cycle in said refresh mode, a refresh cycle regulating means coupled to said second terminal means for receiving said control data signal and producing a control data signal indicative of time intervals corresponding to said time interval represented by said control data signal, a timer means responsive to said control data signal for periodically producing a timing control signal at said time intervals in said refresh mode, and a refresh address generating means responsive to said timing control signal for periodically incrementing an address represented by said refresh address signal in said refresh mode.

Claim 5

The semiconductor dynamic random access memory device as set forth in claim 2, in which said timer means includes an oscillator for generating a periodic signal, a counter for incrementing a count value in response to said periodic signal and generating a multi-bit count signal indicative of said count value, and a divider having a plurality of input nodes respectively supplied with the bits of said multi-bit count signal, a logic gate having a plurality of input nodes and generating said timing control signal when a bit pattern at said input nodes thereof is matched with a reference pattern, and a transfer circuit responsive to said control data signal for selectively transferring said bits of said multi-bit count signal to said input nodes of said logic gate.

Claim 6

The semiconductor dynamic random access memory device as set forth in claim 3, in which said logic gate is a NAND gate, and said reference pattern is constituted by logic "1" level bits.

Claim 7

The semiconductor dynamic random access memory device as set forth in claim 2, in which said refresh cycle regulating means has a default section for maintaining a standard time interval of said refresh cycle, said refresh cycle regulating means producing said control data signal indicative of said standard time interval when said control data is not received in said refresh mode.