Patent US5641698A successfully refreshed from Google Patents.
US5641698A
Expired / Lapsed
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Method of fabricating FET device with double spacer
Assignee: United Microelectronics Corp
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Filing: 1996-04-25
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Granted: 1997-06-24
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Expires: 2016-04-25
Abstract
Abstract An improved FET device in which the hot carrier immunity and current driving capability are improved, and the subthreshold leakage current is minimized. The device has a gate electrode with vertical sidewalls, and a thin layer of SiO 2 over the electrode. A first polysilicon spacer is provided on the vertical sidewalls, with a second overlying oxide spacer over the first spacer. The top portion of the SiO 2 layer between the gate electrode and the polysilicon spacer is made conductive enough to keep the gate electrode and the polysilicon spacer at the same potential. Lightly doped source and drain regions are provided.
Inventors
- 👤 Jengping Lin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 10:55
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/60; H10D30/601; H10D30/605; H10D64/00; H10D64/01; H10D64/021; H10D64/60; H10D64/605; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0147; H10D84/02; H10D84/03; H10D84/038; H10D64/66; Y; Y10; Y10S; Y10S257/00; Y10S257/90
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
167 words
A method of forming a FET comprising the steps of: forming a gate insulating layer on a semiconductor substrate doped to a first conductivity type; forming a polycrystalline silicon gate electrode having vertical sidewalls on the gate insulating layer; forming a SiO 2 layer covering the sidewalls of the gate electrode; forming low concentration portions of source and drain regions in the substrate of a second conductivity type in the substrate using the gate electrode as a mask; depositing a silicon nitride layer on the substrate and gate electrode; etching the silicon nitride layer to form silicon nitride spacers on the SiO 2 layer covering the sidewalls of the gate electrode; depositing a conformal layer of SiO 2 over the substrate and gate electrode; etching the conformal layer of SiO 2 to form spacers over the silicon nitride spacers; and forming higher concentration portions of the source and drain regions of the second conductivity type in the substrate using the electrode and sidewall spacers as a mask.
Claim 2
Independent Claim
167 words
A method of forming a FET comprising the steps of: forming a gate insulating layer on a semiconductor substrate doped to a first conductivity type; forming a polycrystalline silicon gate electrode having vertical sidewalls on the gate insulating layer; forming a SiO 2 layer covering the sidewalls of the gate electrode; forming low concentration portions of source and drain regions in the substrate of a second conductivity type in the substrate using the gate electrode as a mask; depositing a silicon nitride layer on the substrate and gate electrode; etching the silicon nitride layer to form silicon nitride spacers on the SiO 2 layer covering the sidewalls of the gate electrode; depositing a conformal layer of SiO 2 over the substrate and gate electrode; etching the conformal layer of SiO 2 to form spacers over the silicon nitride spacers; and forming higher concentration portions of the source and drain regions of the second conductivity type in the substrate using the electrode and sidewall spacers as a mask.
Claim 3
Dependent Claim
20 words
The method of claim 1 wherein the silicon nitride layer has a thickness of between about 200 to 1000 Angstroms.
Claim 4
Dependent Claim
22 words
The method of claim 2 wherein the thickness of the conformal layer of SiO 2 is between about 500 to 2000 Angstroms.
Claim 5
Dependent Claim
26 words
The method of claim 1 wherein the SiO 2 layer covering the sidewalls of the gate electrode is formed by thermal oxidation of the gate electrode.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-06-23 | 2000-12-23 | 2001-06-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-06-23 | 2004-12-23 | 2005-06-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-06-23 | 2008-12-23 | 2009-06-24 | $7700.00 | Window Closed / Lapsed |