Current mode null convention threshold gate

Claim 2

A NULL convention threshold gate comprising: a plurality of input signal lines, each having an asserted stated and a NULL state; an output signal line having an asserted state and a NULL state; assertion means for placing the output signal line in an asserted state when the number of asserted input signal lines exceeds a threshold number; and means for holding the output signal line in an asserted state until all input signal lines have returned to NULL; wherein an asserted state is characterized by a first current state, and a NULL state is characterized by a second current state.

Claim 3

A NULL convention threshold gate comprising: a plurality of input signal lines, each having an asserted state and a NULL state; an output signal line having an asserted state and a NULL state; a first sub-circuit for placing the output signal line into the asserted state when the number of asserted input signal lines exceeds a threshold number; and a second sub-circuit for placing the output signal line into the NULL state when all inputs have returned to NULL; wherein an asserted state is characterized by a first current state, and a NULL state is characterized by a second current state.

Claim 4

A NULL convention threshold gate comprising: a plurality of input signal lines, each having an asserted state and a NULL state; an output signal line having an asserted state and a NULL state; a first sub-circuit for placing the output signal line into the asserted state when the number of asserted input signal lines exceeds a threshold number; and a second sub-circuit for placing the output signal line into the NULL state when all inputs have returned to NULL; wherein an asserted state is characterized by a first current state, and a NULL state is characterized by a second current state.

Claim 5

A combinational circuit comprising a plurality of interconnected NULL convention threshold gates, each NULL convention threshold gate comprising: a first sub-circuit for placing the output signal line into the asserted state when the number of asserted input signal lines exceeds a threshold number; and a second sub-circuit for placing the output signal lines into the NULL state when all inputs have returned to NULL; wherein an asserted state is characterized by a first current state, and a NULL state is characterized by a second current state.

Claim 6

A combinational circuit comprising a plurality of interconnected NULL convention threshold gates, each NULL convention threshold gate comprising: a first sub-circuit for placing the output signal line into the asserted state when the number of asserted input signal lines exceeds a threshold number; and a second sub-circuit for placing the output signal lines into the NULL state when all inputs have returned to NULL; wherein an asserted state is characterized by a first current state, and a NULL state is characterized by a second current state.

Claim 7

A current mode m-of-n NULL convention threshold gate with hysteresis comprising: a plurality of n input signal lines, each line having an asserted state and a NULL state, wherein the asseted state is characterized by a first current state, and the NULL state is characterized by a second current state; an output signal line having an asserted state and a NULL state; an output circuit switchably generating an asserted output signal and a NULL output signal on the output signal line; and a transistor network switching the output signal line from the asserted state to the NULL state when a number m of input signal lines changes from the NULL state to the asserted state, m being less than n, said switching circuit further holding the output signal line in an asserted state until all input signal lines return to NULL.

Claim 8

A current mode m-of-n NULL convention threshold gate with hysteresis comprising: a plurality of n input signal lines, each line having an asserted state and a NULL state, wherein the asseted state is characterized by a first current state, and the NULL state is characterized by a second current state; an output signal line having an asserted state and a NULL state; an output circuit switchably generating an asserted output signal and a NULL output signal on the output signal line; and a transistor network switching the output signal line from the asserted state to the NULL state when a number m of input signal lines changes from the NULL state to the asserted state, m being less than n, said switching circuit further holding the output signal line in an asserted state until all input signal lines return to NULL.

Claim 9

The gate of claim 4 further including a feedback circuit providing a feedback signal to the transistor network, said feedback signal varying in accordance with the state of the output signal line.

Claim 10

The gate of claim 5 wherein the feedback circuit includes a current-generating transistor operating in parallel with said output circuit and generating a feedback current signal on an input signal line.

Claim 11

The gate of claim 4 wherein the transistor network comprises: a signal node receiving currents from the plurality of input signal lines; and a trigger circuit triggering the output circuit to generate an asserted output when a collective current traversing the signal node exceeds a threshold current.

Claim 12

The gate of claim 4 wherein the output circuit includes at least one current-providing output transistor responsive to the switching circuit.

Claim 13

The gate of claim 4 wherein the output circuit includes a plurality of current-providing output transistors responsive to the switching circuit and generating a plurality of substantially equal output currents.

Claim 14

The gate of claim 4 wherein the transistor network includes current mode MOS devices.

Claim 15

The gate of claim 4 wherein a first group of input signal lines forms a first mutually exclusive assertion group in which only one signal line is asserted at a time.

Claim 16

The gate of claim 4 wherein a plurality of groups of input signal lines form a plurality of mutually exclusive assertion groups in each of which only one signal line is asserted at a time.

Claim 17

The gate of claim 12 wherein the threshold number m equals the number of mutually exclusive assertion groups.

Claim 18

A current mode m-of-n NULL convention threshold gate with hysteresis comprising: a plurality of n input signal lines, each line having an asserted state and a NULL state, wherein the asserted state is characterized by a first current state and the NULL state is characterized by a second NULL state; an output signal line having an asserted state and a NULL state; output means for switchably placing the output signal line in an asserted state and a NULL state; and hysteresis means for (1) placing the output means into the asserted state when a number of asserted input signal lines exceeds a threshold number m, said threshold value m less than n, (2) holding the output means in the asserted state when the number of asserted inputs signal lines falls to below the threshold number m while remaining greater than zero, and (3) placing the output means into the NULL state when all input signal lines are NULL.

Claim 19

A current mode m-of-n NULL convention threshold gate with hysteresis comprising: a plurality of n input signal lines, each line having an asserted state and a NULL state, wherein the asserted state is characterized by a first current state and the NULL state is characterized by a second NULL state; an output signal line having an asserted state and a NULL state; output means for switchably placing the output signal line in an asserted state and a NULL state; and hysteresis means for (1) placing the output means into the asserted state when a number of asserted input signal lines exceeds a threshold number m, said threshold value m less than n, (2) holding the output means in the asserted state when the number of asserted inputs signal lines falls to below the threshold number m while remaining greater than zero, and (3) placing the output means into the NULL state when all input signal lines are NULL.

Claim 20

The gate of claim 14 wherein the hysteresis means includes feedback means for providing a feedback signal to an input signal line, said feedback signal varying in accordance with the state of the output signal line.

Claim 21

The gate of claim 14 wherein the hysteresis means includes threshold means for generating a control signal having a first state when the collective current on the input signal lines exceeds a threshold value and having a second state when the collective current on the input signal lines is less than a threshold value.

Claim 22

The gate of claim 14 wherein the output means includes a first current generating means generating a current in response to the hysteresis means.

Claim 23

The gate of claim 14 wherein the output means includes a plurality of current generating means generating a plurality of substantially equal currents in response to the hysteresis.

Claim 24

The gate of claim 14 wherein a first group of input signal lines forms a first mutually exclusive assertion group in which only one signal line is asserted at a time.

Claim 25

The gate of claim 14 wherein a plurality of groups of input signal lines form mutually exclusive assertion groups, wherein only one signal line of a mutually exclusive assertion group is asserted at a time.