Method of making a low capacitance antifuse having a pillar located between the first and second metal layers

Claim 1

A method for forming an antifuse for use in user-programmable integrated circuitry, comprising the steps of: forming a first connection metal layer on a first dielectric layer; forming a conductive pillar on said first connection metal layer and directly over said first dielectric layer, whereby said conductive pillar is narrower than said first connection metal layer; forming a second dielectric layer on said first connection metal layer, surrounding said conductive pillar, such that the top of said conductive pillar remains exposed; forming and patterning a layer of antifuse material on said second dielectric layer, in contact with the exposed portion of the conductive pillar; and forming and patterning a second connection metal layer, on said antifuse material; whereby the separation between said first and second connection metal layers is increased, in order to decrease the capacitance of the device.

Claim 2

A method for forming an antifuse for use in user-programmable integrated circuitry, comprising the steps of: forming a first connection metal layer on a first dielectric layer; forming a conductive pillar on said first connection metal layer and directly over said first dielectric layer, whereby said conductive pillar is narrower than said first connection metal layer; forming a second dielectric layer on said first connection metal layer, surrounding said conductive pillar, such that the top of said conductive pillar remains exposed; forming and patterning a layer of antifuse material on said second dielectric layer, in contact with the exposed portion of the conductive pillar; and forming and patterning a second connection metal layer, on said antifuse material; whereby the separation between said first and second connection metal layers is increased, in order to decrease the capacitance of the device.