US5639684A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making a low capacitance antifuse having a pillar located between the first and second metal layers
Assignee: Texas Instruments Inc
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Filing: 1995-06-07
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Granted: 1997-06-17
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Expires: 2015-06-07
Abstract
Abstract A low-capacitance antifuse (34 or 76) is provided for use in user-programmable integrated circuitry. The antifuse includes first (38 or 80) connection metal layers and second (54 or 94) connection metal layers. Between the metal layers is dielectric layer (52 or 82), and between the dielectric layer and at least one of the metal layers is a conductive layer in the form of pillar (40) or stack (81). The pillar or stack extends the separation between the metal layers thereby decreasing the capacitance of the antifuse.
Inventors
- 👤 Siang Ping Kwok
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 12:52
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/064; H10W20/065
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
139 words
A method for forming an antifuse for use in user-programmable integrated circuitry, comprising the steps of: forming a first connection metal layer on a first dielectric layer; forming a conductive pillar on said first connection metal layer and directly over said first dielectric layer, whereby said conductive pillar is narrower than said first connection metal layer; forming a second dielectric layer on said first connection metal layer, surrounding said conductive pillar, such that the top of said conductive pillar remains exposed; forming and patterning a layer of antifuse material on said second dielectric layer, in contact with the exposed portion of the conductive pillar; and forming and patterning a second connection metal layer, on said antifuse material; whereby the separation between said first and second connection metal layers is increased, in order to decrease the capacitance of the device.
Claim 2
Independent Claim
139 words
A method for forming an antifuse for use in user-programmable integrated circuitry, comprising the steps of: forming a first connection metal layer on a first dielectric layer; forming a conductive pillar on said first connection metal layer and directly over said first dielectric layer, whereby said conductive pillar is narrower than said first connection metal layer; forming a second dielectric layer on said first connection metal layer, surrounding said conductive pillar, such that the top of said conductive pillar remains exposed; forming and patterning a layer of antifuse material on said second dielectric layer, in contact with the exposed portion of the conductive pillar; and forming and patterning a second connection metal layer, on said antifuse material; whereby the separation between said first and second connection metal layers is increased, in order to decrease the capacitance of the device.
Claim 3
Dependent Claim
21 words
A method as in claim 1, wherein said first connection metal layer has a uniform thickness of 4,000 to 5,000 Angstroms.
Claim 4
Dependent Claim
20 words
A method as in claim 2, wherein said second dielectric layer has a uniform thickness of at least 10,000 Angstroms.
Claim 5
Dependent Claim
20 words
A method as in claim 3, wherein said antifuse material has a uniform thickness of about 1,000 to 2,000 Angstroms.
Claim 6
Dependent Claim
22 words
A method as in claim 4, wherein said second connection metal layer has a uniform thickness of about 4,000 to 5,000 Angstroms.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-06-16 | 2000-12-16 | 2001-06-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-06-16 | 2004-12-16 | 2005-06-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-06-16 | 2008-12-16 | 2009-06-17 | $7700.00 | Window Closed / Lapsed |