Patent FR846072A successfully refreshed from Google Patents.
Patent US5638525A successfully refreshed from Google Patents.
US5638525A
Expired / Lapsed
US
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Processor capable of executing programs that contain RISC and CISC instructions
Assignee: Intel Corp
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Filing: 1995-02-10
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Granted: 1997-06-10
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Expires: 2015-02-10
Abstract
Abstract A data processor is described. The data processor is capable of decoding and executing the first instruction of a first instruction set and the second instruction of a second instruction set wherein the first instruction and the second instruction originate from a single computer program. Alternatively, the data processor can also execute a first instruction of a first instruction set in a first instruction set mode, receive a first interruption indication in the first instruction set mode, service the first interruption indication in a second instruction set mode, return to the first instruction set mode, receive a second interruption indication in the first instruction set mode, and service the second interruption indication in the first instruction set mode.
Inventors
- 👤 Gary N. Hammond
- 👤 Kevin C. Kahn
- 👤 Donald B. Alpert
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 05:01
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/30; G06F9/38; G06F9/3818; G06F9/3822; G06F9/30003; G06F9/3004; G06F9/30043; G06F9/3005; G06F9/30054; G06F9/30076; G06F9/30098; G06F9/3012; G06F9/30123; G06F9/3017; G06F9/30174; G06F9/30181; G06F9/30189; G06F9/30196; G06F9/32; G06F9/322; G06F9/323; G06F9/44; G06F9/455; G06F9/45533
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
142 words
A processor for running a program that includes instructions of first and second instruction sets, wherein said first instruction set is a complex instruction set computer architecture (CISC) type and said second instruction set is a reduced instruction set computer architecture (RISC) type, said data processor comprising: one or more cache memories that store a sequence of instructions of said program; an instruction processing unit coupled to said one or more cache memories that decodes and executes a first instruction in said sequence from said first instruction set and a second instruction in said sequence from said second instruction set; first and second register files respectively associated with said first and second instruction sets, wherein data associated with said first instruction is stored in said first register file, and data associated with said second instruction is stored in said second register file.
Claim 2
Dependent Claim
142 words
A processor for running a program that includes instructions of first and second instruction sets, wherein said first instruction set is a complex instruction set computer architecture (CISC) type and said second instruction set is a reduced instruction set computer architecture (RISC) type, said data processor comprising: one or more cache memories that store a sequence of instructions of said program; an instruction processing unit coupled to said one or more cache memories that decodes and executes a first instruction in said sequence from said first instruction set and a second instruction in said sequence from said second instruction set; first and second register files respectively associated with said first and second instruction sets, wherein data associated with said first instruction is stored in said first register file, and data associated with said second instruction is stored in said second register file.
Claim 3
Dependent Claim
103 words
The processor of claim 1 wherein said instruction processing unit comprises: a first decoder coupled to said one or more cache memories that decodes said first instruction; a second decoder coupled to said one or more cache memories that decodes said second instruction; a multiplexor having an output and inputs coupled to said first and second decoders; an execution unit coupled to said output of said multiplexor that executes the first and second instructions, said execution unit writing a first result of said first instruction to said first register file, and a second result of said second instruction to said second register file.
Claim 4
Dependent Claim
56 words
The processor of claim 2 wherein said program includes a switch instruction and said instruction processing unit further comprises: an instruction set mode selector (ISMS) coupled to said first and second decoders and to said multiplexor, wherein said ISMS generates a select signal that selects said output of said multiplexor in response to said switch instruction.
Claim 5
Dependent Claim
17 words
The processor of claim 1 wherein said first instruction comprises 32-bits and said second instruction comprises 64-bits.
Claim 6
Dependent Claim
130 words
A computer system comprising; a bus; an external memory coupled to said bus; a microprocessor coupled to said external memory and said bus, said microprocessor including: first and second register files; an instruction cache that stores first and second instructions of a program; a first decoder coupled to said instruction cache that decodes said first instruction; a second decoder coupled to said instruction cache that decodes said second instruction; a multiplexor having inputs coupled to said first and second decoders, and an output; an execution unit coupled to said output of said multiplexor that executes said first and second instructions, with a first result of said first instruction being written to said first register file, and a second result of said second instruction being written to said second register file.
Claim 7
Dependent Claim
130 words
A computer system comprising; a bus; an external memory coupled to said bus; a microprocessor coupled to said external memory and said bus, said microprocessor including: first and second register files; an instruction cache that stores first and second instructions of a program; a first decoder coupled to said instruction cache that decodes said first instruction; a second decoder coupled to said instruction cache that decodes said second instruction; a multiplexor having inputs coupled to said first and second decoders, and an output; an execution unit coupled to said output of said multiplexor that executes said first and second instructions, with a first result of said first instruction being written to said first register file, and a second result of said second instruction being written to said second register file.
Claim 8
Dependent Claim
39 words
The computer system of claim 5 wherein said execution unit comprises: a first execution unit coupled to said first decoder that executes said first instruction; a second execution unit coupled to said second decode that executes said second instruction.
Claim 9
Dependent Claim
54 words
The computer system of claim 6 wherein said microprocessor further comprises: a translator unit coupled to said instruction cache, said translator unit being adapted to translate said first instruction of said first instruction set into corresponding instruction(s) of said second instruction set, said instruction cache storing said corresponding instruction(s) of said second instruction set.
Claim 10
Dependent Claim
34 words
The computer system of claim 5 wherein said first instruction set is a complex instruction set computer architecture (CISC) type and said second instruction set is a reduced instruction set computer architecture (RISC) type.
Claim 11
Dependent Claim
84 words
In a processor having first and second instruction set operating modes, a method for executing a program that contains instructions of first and second instruction sets, said method comprising steps of: (a) executing a first instruction of said first instruction set while said processor is in said first instruction set operating mode; (b) receiving a first interruption indication; (c) servicing said first interruption indication while said processor is in said second instruction set operating mode; (d) returning to said first instruction set operating mode.
Claim 12
Dependent Claim
84 words
In a processor having first and second instruction set operating modes, a method for executing a program that contains instructions of first and second instruction sets, said method comprising steps of: (a) executing a first instruction of said first instruction set while said processor is in said first instruction set operating mode; (b) receiving a first interruption indication; (c) servicing said first interruption indication while said processor is in said second instruction set operating mode; (d) returning to said first instruction set operating mode.
Claim 13
Dependent Claim
25 words
The method of claim 9 wherein said first instruction set is a CISC instruction set and said second instruction set is a RISC instruction set.
Claim 14
Dependent Claim
25 words
The method of claim 9 wherein said first instruction set is a RISC instruction set and said second instruction set is a CISC instruction set.
Claim 15
Dependent Claim
27 words
The method of claim 9 wherein said first instruction set is a 64-bit instruction set and said second instruction set is a 16 or 32-bit instruction set.
Claim 16
Dependent Claim
27 words
The method of claim 9 wherein said first instruction set is a 16 or 32-bit instruction set and said second instruction set is a 64-bit instruction set.
Claim 17
Dependent Claim
75 words
In a processor, a method for executing a program that contains RISC and CISC instructions comprising steps of: (a) executing a first instruction in said program, said first instruction being one of said CISC instructions; (b) executing a switch instruction, the switch instruction including a value that indicates a location of a next instruction in said program; and (c) executing said next instruction in said program, said next instruction being one of said RISC instructions.
Claim 18
Dependent Claim
75 words
In a processor, a method for executing a program that contains RISC and CISC instructions comprising steps of: (a) executing a first instruction in said program, said first instruction being one of said CISC instructions; (b) executing a switch instruction, the switch instruction including a value that indicates a location of a next instruction in said program; and (c) executing said next instruction in said program, said next instruction being one of said RISC instructions.
Claim 19
Dependent Claim
26 words
The method of claim 14 wherein step (b) further comprises the step of: converting, by said processor, said value into and address of said next instruction.
Claim 20
Dependent Claim
21 words
The method of claim 14 wherein said RISC instructions comprise 64-bit instructions and said CISC instructions comprises 16 or 32-bit instructions.
Claim 21
Dependent Claim
59 words
In a processor, a method for executing instructions of a computer program comprising steps of: (a) executing a first instruction of a first instruction set; (b) executing a first switch instruction that changes said processor from a first instruction set mode to a second instruction set mode of operation; (c) executing a second instruction of a second instruction set.
Claim 22
Dependent Claim
59 words
In a processor, a method for executing instructions of a computer program comprising steps of: (a) executing a first instruction of a first instruction set; (b) executing a first switch instruction that changes said processor from a first instruction set mode to a second instruction set mode of operation; (c) executing a second instruction of a second instruction set.
Claim 23
Dependent Claim
45 words
The method of claim 17 further comprising the additional steps of: (d) executing a second switch instruction that changes said processor from said second instruction set mode to said first instruction set mode of operation; (e) executing a second instruction of said first instruction set.
Claim 24
Dependent Claim
30 words
The method of claim 17 wherein step (e) moves a data value from a register associated with said first instruction set to a register associated with said second instruction set.
References Cited (Backward Citations)
US4839797A
Cited
US5481684A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-06-09 | 2000-12-09 | 2001-06-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-06-09 | 2004-12-09 | 2005-06-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-06-09 | 2008-12-09 | 2009-06-10 | $7700.00 | Window Closed / Lapsed |