Patent US5636368A successfully refreshed from Google Patents.
US5636368A
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Method for programming complex PLD having more than one function block type
Assignee: Xilinx Inc
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Filing: 1994-12-23
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Granted: 1997-06-03
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Expires: 2014-12-23
Abstract
Abstract A method for programming programmable logic devices (PLDs) having multiple function block types to implement a logic function, whereby the logic function is mapped into one of the function block types before being mapped into the remaining function block types. In one embodiment, a PLD containing both "fast" function blocks (FFBs) and "high density" function blocks (HDFBs) are programmed such that the FFBs are programmed prior to the HDFBs. This method maximizes the overall speed of an implemented logic function.
Inventors
- 👤 David A. Harrison
- 👤 Joshua M. Silver
- 👤 Soren T. Soe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 22:15
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/34
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
129 words
A method for configuring a programmable logic device to implement a logic function, the method comprising the steps of: identifying portions of said logic function which qualify for implementation in a first type of function block, wherein said first type of function block provides a first speed and density; splitting the qualified portions of said logic function into a plurality of sub-portions such that each sub-portion is implementable in said first type of function block; mapping said qualified portions of said logic function into said first type of function block until said first type of function block is fully utilized; and mapping unmapped qualified portions of said logic function into a second type of function block, wherein said second type of function block provides a second speed and density.
Claim 2
Independent Claim
129 words
A method for configuring a programmable logic device to implement a logic function, the method comprising the steps of: identifying portions of said logic function which qualify for implementation in a first type of function block, wherein said first type of function block provides a first speed and density; splitting the qualified portions of said logic function into a plurality of sub-portions such that each sub-portion is implementable in said first type of function block; mapping said qualified portions of said logic function into said first type of function block until said first type of function block is fully utilized; and mapping unmapped qualified portions of said logic function into a second type of function block, wherein said second type of function block provides a second speed and density.
Claim 3
Dependent Claim
22 words
The method of claim 1 wherein said step of identifying includes reformulating a plurality of Boolean equations associated with said logic function.
Claim 4
Dependent Claim
27 words
The method of claim 2 wherein said reformulating includes designating if any equations of said logic function are user-identified as being implementable in said fast function block.
Claim 5
Dependent Claim
31 words
The method of claim 3 wherein if any fast equations are designated, then said reformulating further includes determining if sufficient clock resources are available to support all the designated fast equations.
Claim 6
Dependent Claim
25 words
The method of claim 4 wherein if sufficient clock resources are available, then said reformulating further includes determining if sufficient fast output enable signals exist.
Claim 7
Dependent Claim
29 words
The method of claim 5 wherein if sufficient fast output enable signals exist or if no fast equations are designated, then said reformulating further includes performing input register optimization.
Claim 8
Dependent Claim
22 words
The method of claim 6 wherein after said input register optimization, said reformulating includes determining if any fast clock signals are undefined.
Claim 9
Dependent Claim
24 words
The method of claim 7 wherein if any fast clock signals are undefined, then said reformulating further includes performing a fast clock signal optimization.
Claim 10
Dependent Claim
35 words
The method of claim 8 wherein if fast clock signal optimization is performed or if no fast clock signals are undefined, then said reformulating further includes determining if any fast output enable signals are undefined.
Claim 11
Dependent Claim
24 words
The method of claim 9 wherein if any fast output enable signals are undefined, then said reformulating includes performing an output enable signal optimization.
Claim 12
Dependent Claim
29 words
The method of claim 10 wherein if output enable signal optimization is performed or if no fast output enable signals are undefined, then said reformulating includes performing logic collapsing.
Claim 13
Dependent Claim
15 words
The method of claim 11 wherein after said logic collapsing, said reformulating includes minimizing logic.
Claim 14
Dependent Claim
22 words
The method of claim 1 wherein said splitting includes determining the number of product terms in an equation of said logic function.
Claim 15
Dependent Claim
23 words
The method of claim 13 wherein said splitting further includes determining the number of input signals in an equation of said logic function.
Claim 16
Dependent Claim
27 words
The method of claim 1 further including the step of determining which equations of said logic function are formed using an AND array in an interconnect matrix.
Claim 17
Independent Claim
128 words
A method for configuring a programmable logic device to implement a logic function, the method comprising the steps of: identifying portions of said logic function which qualify for implementation in a first type of function block; splitting the qualified portions of said logic function into a plurality of sub-portions such that each sub-portion is implementable in said first type of function block; mapping said qualified portions of said logic function into said first type of function block until said first type of function block is fully utilized; and mapping unmapped qualified portions of said logic function into a second type of function block, wherein said first type of function block is a fast function block and said second type of function block is a high density function block.
Claim 18
Independent Claim
128 words
A method for configuring a programmable logic device to implement a logic function, the method comprising the steps of: identifying portions of said logic function which qualify for implementation in a first type of function block; splitting the qualified portions of said logic function into a plurality of sub-portions such that each sub-portion is implementable in said first type of function block; mapping said qualified portions of said logic function into said first type of function block until said first type of function block is fully utilized; and mapping unmapped qualified portions of said logic function into a second type of function block, wherein said first type of function block is a fast function block and said second type of function block is a high density function block.
Claim 19
Dependent Claim
18 words
The method of claim 16 wherein said second type of function block includes an Arithmetic Logic Unit (ALU).
Claim 20
Dependent Claim
17 words
The method of claim 17 wherein said ALU operates in a first mode and a second mode.
Claim 21
Dependent Claim
25 words
The method of claim 18 wherein said first mode includes said ALU programmably generating a Boolean function based on the input signals to said ALU.
Claim 22
Dependent Claim
25 words
The method of claim 18 wherein said second mode includes said ALU programmably generating an arithmetic function based on the input signals to said ALU.
Claim 23
Independent Claim
147 words
A method for configuring a programmable logic device to implement a logic function, the method comprising the steps of: identifying portions of said logic function which qualify for implementation in a first type of function block; splitting the qualified portions of said logic function into a plurality of sub-portions such that each sub-portion is implementable in said first type of function block, wherein said splitting includes determining the number of product terms and the number of input signals in an equation of said logic function, wherein said splitting further includes determining the polarity of an equation of said logic function associated with a high density block; mapping said qualified portions of said logic function into said first type of function block until said first type of function block is fully utilized; and mapping unmapped qualified portions of said logic function into a second type of function block.
Claim 24
Independent Claim
147 words
A method for configuring a programmable logic device to implement a logic function, the method comprising the steps of: identifying portions of said logic function which qualify for implementation in a first type of function block; splitting the qualified portions of said logic function into a plurality of sub-portions such that each sub-portion is implementable in said first type of function block, wherein said splitting includes determining the number of product terms and the number of input signals in an equation of said logic function, wherein said splitting further includes determining the polarity of an equation of said logic function associated with a high density block; mapping said qualified portions of said logic function into said first type of function block until said first type of function block is fully utilized; and mapping unmapped qualified portions of said logic function into a second type of function block.
Claim 25
Dependent Claim
20 words
The method of claim 21 wherein said splitting further includes forming a linking equation for linking a plurality of sub-portions.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-06-02 | 2000-12-02 | 2001-06-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-06-02 | 2004-12-02 | 2005-06-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-06-02 | 2008-12-02 | 2009-06-03 | $7700.00 | Window Closed / Lapsed |