Scan register with decoupled scan routing

Claim 2

A scan register comprising: circuitry for receiving a data signal; circuitry for receiving a scan signal; circuitry, coupled to said circuitry for receiving said data signal, for outputting said data signal; and circuitry, coupled to said circuitry for receiving said scan signal, for outputting said scan signal, wherein said outputting circuitry for said data signal is separate from said outputting circuitry for said scan signal.

Claim 3

The scan register as recited in claim 1, further comprising: circuitry for passing said data signal and said scan signal, wherein said outputting circuitry for said data signal and said outputting circuitry for said scan signal are both coupled to said passing circuitry.

Claim 4

The scan register as recited in claim 1, wherein said outputting circuitry for said scan signal includes circuitry for selectively enabling and disabling said outputting circuitry for said scan signal.

Claim 5

The scan register as recited in claim 3, wherein said circuitry for selectively enabling and disabling said outputting circuitry for said scan signal further comprises a circuit controlled by receipt of a scan enable signal that is activated when a scan operation is enabled.

Claim 6

The scan register as recited in claim 1, wherein said outputting circuitry for said data signal further comprises: a first inverter coupled to said circuitry for receiving said data signal; a second inverter coupled to said first inverter; and a third inverter coupled to said first and second inverters, and wherein said outputting circuitry for said scan signal further comprises: a logic circuit coupled to said first, second and third inverters.

Claim 7

The scan register as recited in claim 5, wherein said logic circuit is a fourth inverter that is responsive to a scan enable signal.

Claim 8

The scan register as recited in claim 6, wherein said scan enable signal is operable for disabling said fourth inverter.

Claim 9

A processor comprising: logic circuitry comprising a plurality of scan registers; and circuitry for enabling and disabling a scan operation through said plurality of scan registers, wherein a scan register within said plurality of scan registers comprises: circuitry for outputting a data signal; circuitry for receiving a scan signal; circuitry for outputting said scan signal; and circuitry for decoupling said circuitry for outputting said scan signal from said circuitry for outputting said data signal.

Claim 10

A processor comprising: logic circuitry comprising a plurality of scan registers; and circuitry for enabling and disabling a scan operation through said plurality of scan registers, wherein a scan register within said plurality of scan registers comprises: circuitry for outputting a data signal; circuitry for receiving a scan signal; circuitry for outputting said scan signal; and circuitry for decoupling said circuitry for outputting said scan signal from said circuitry for outputting said data signal.

Claim 11

The processor as recited in claim 8, wherein said circuitry for outputting said scan signal is separate from said circuitry for outputting said data signal.

Claim 12

The processor as recited in claim 8, wherein said decoupling circuitry further comprises a device operable for receiving an activation signal from said circuitry for enabling and disabling said scan operation, wherein said activation signal is dependent upon said scan operation and operates to deactivate said device when said scan operation is disabled.

Claim 13

A register comprising: a master portion operable for receiving a data signal, a scan signal, a data clock signal, and a scan clock signal; and a slave portion operable for receiving said scan signal or said data signal, wherein said slave portion further comprises: a first inverter coupled between said master portion and a node; a second inverter coupled to said node; circuitry, coupled to said second inverter, for outputting said data signal; a third inverter coupled to said circuitry for outputting said data signal and said node; circuitry for outputting said scan signal; and a logic circuit coupled between said node and said circuitry for outputting said scan signal.

Claim 14

A register comprising: a master portion operable for receiving a data signal, a scan signal, a data clock signal, and a scan clock signal; and a slave portion operable for receiving said scan signal or said data signal, wherein said slave portion further comprises: a first inverter coupled between said master portion and a node; a second inverter coupled to said node; circuitry, coupled to said second inverter, for outputting said data signal; a third inverter coupled to said circuitry for outputting said data signal and said node; circuitry for outputting said scan signal; and a logic circuit coupled between said node and said circuitry for outputting said scan signal.

Claim 15

The register as recited in claim 11, wherein said logic circuit includes circuitry operable to receive an activation signal.

Claim 16

The register as recited in claim 12, wherein said activation signal operates to couple and decouple said circuitry for outputting said scan signal from said node.

Claim 17

The register as recited in claim 13, wherein said logic circuit is a fourth inverter.