US5596584A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Single clock scan latch
Assignee: STMicroelectronics Ltd Great Britain
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Filing: 1995-08-24
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Granted: 1997-01-21
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Expires: 2015-08-24
Abstract
Abstract A half-latch for a scan latch is described. The half-latch has an input terminal for receiving an input signal a first control terminal for receiving a clock signal and an output terminal. When enabled, the half-latch adopts a data transfer state in which it transmits a signal from its input terminal to its output terminal. Alternatively, the half-latch can adopt a data holding state in which a signal is stored on the output terminal, these states being selected in dependence on the state of the clock signal. The half-latch described herein has a second control terminal which receives the control signal to selectively disable the half-latch. This allows a common clock signal to be used when a scan latch is constructed using these half-latches.
Inventors
- 👤 Robert Warren
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:26
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/2205; G06F11/2236; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318541; G01R31/318552; H; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/037; H03K3/0375
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
90 words
A half-latch having an input terminal connected to receive an input signal, a first control terminal connected to receive a clock signal, and an output terminal, the half-latch being operable, when enabled, to adopt a data transfer state to transmit a signal from its input terminal to its output terminal or a data holding state to store the signal on the output terminal in dependence on the state of said clock signal, the half-latch comprising a second control terminal connected to receive a control signal to selectively disable the half-latch.
Claim 2
Dependent Claim
90 words
A half-latch having an input terminal connected to receive an input signal, a first control terminal connected to receive a clock signal, and an output terminal, the half-latch being operable, when enabled, to adopt a data transfer state to transmit a signal from its input terminal to its output terminal or a data holding state to store the signal on the output terminal in dependence on the state of said clock signal, the half-latch comprising a second control terminal connected to receive a control signal to selectively disable the half-latch.
Claim 3
Dependent Claim
22 words
A half-latch according to claim 1 wherein the first control terminal comprises a first pass gate connected to receive said clock signal.
Claim 4
Dependent Claim
24 words
A half-latch according to claim 1 or 2 wherein the second control terminal comprises a second pass gate connected to receive said control signal.
Claim 5
Dependent Claim
19 words
A half-latch according to claim 1 which comprises a storage node for storing the signal on the output terminal.
Claim 6
Dependent Claim
35 words
A half-latch according to claim 4 wherein the storage node comprises first and second inverters in a back-to-back configuration, one of the inverters being forwardly connected and being stronger than the other of the inverters.
Claim 7
Dependent Claim
221 words
A scan latch comprising: a multiplexor having a data input terminal connected to receive a data input signal, a scan input terminal connected to receive a scan input signal, a control terminal connected to receive a control signal, and an output terminal; a capture half-latch having an input terminal connected to the output terminal of the multiplexor, a clock terminal connected to receive a clock signal, and an intermediate output terminal; a release half-latch having an input terminal, a control terminal connected to receive a control signal, and a scan output terminal; and an update half-latch having an input terminal, a control terminal connected to receive a control signal and a data output terminal; wherein the multiplexor is controlled by the control signal on its control terminal to selectively apply the data input signal or the scan input signal to the input terminal of the capture half-latch, and the scan latch further comprises a clocking element having a clock terminal connected between the intermediate output terminal of the capture half-latch and the input terminals of the release half-latch and the update half-latch, said clock terminal being arranged to receive a clock signal for controlling the release half-latch or the update half-latch, the state of the update half-latch and release half-latch being selectively enabled by the control signals on their control terminals.
Claim 8
Dependent Claim
221 words
A scan latch comprising: a multiplexor having a data input terminal connected to receive a data input signal, a scan input terminal connected to receive a scan input signal, a control terminal connected to receive a control signal, and an output terminal; a capture half-latch having an input terminal connected to the output terminal of the multiplexor, a clock terminal connected to receive a clock signal, and an intermediate output terminal; a release half-latch having an input terminal, a control terminal connected to receive a control signal, and a scan output terminal; and an update half-latch having an input terminal, a control terminal connected to receive a control signal and a data output terminal; wherein the multiplexor is controlled by the control signal on its control terminal to selectively apply the data input signal or the scan input signal to the input terminal of the capture half-latch, and the scan latch further comprises a clocking element having a clock terminal connected between the intermediate output terminal of the capture half-latch and the input terminals of the release half-latch and the update half-latch, said clock terminal being arranged to receive a clock signal for controlling the release half-latch or the update half-latch, the state of the update half-latch and release half-latch being selectively enabled by the control signals on their control terminals.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-01-21 | 2000-07-22 | 2001-01-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-01-21 | 2004-07-22 | 2005-01-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-01-21 | 2008-07-22 | 2009-01-21 | $7700.00 | Window Closed / Lapsed |