Patent US5635859A successfully refreshed from Google Patents.
US5635859A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Level converting circuit
Assignee: Fujitsu Ltd
•
Filing: 1993-03-03
•
Granted: 1997-06-03
•
Expires: 2013-03-03
Abstract
Abstract The present invention provides a level converting circuit comprising: a differential output transistor circuit for amplifying a difference between two mutually complementary input logic signals; a first output transistor circuit for outputting an inverted output logic signal based on a signal output by the differential output transistor circuit; and a second output transistor circuit for outputting an uninverted output logic signal based on a signal output by the differential output transistor circuit, wherein the first output transistor circuit further comprises first and second field-effect transistors and the second output transistor circuit further comprises third and fourth field-effect transistors. The differential output transistor circuit comprises a combination of first, second, third, fourth and fifth bais components which are each resistive element or a field-effect transistors. Assume that the uninverted logic output signal is lowered to an `L` level at a potential lower than that of the second differential output point. In this state, the fourth field-effect transistor of the second output transistor circuit performs a reversed operation, causing a drain current to flow to the output unit. Accordingly, the potential of the second differential output point is pulled down, displaying a feedback function that lowers back the gate potential of the third field-effect transistor of the second output transistor circuit and abruptly pulling up its `L` to `H` level.
Inventors
- 👤 Noboru Yokota
- 👤 Noriaki Kogawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 13:07
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018521; H03K19/018528
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
306 words
A level converting circuit characterized by comprising: a differential output transistor circuit for amplifying a difference between two mutually complementary input logic signals; a first output transistor circuit for outputting an inverted output logic signal based on a signal output by said differential output transistor circuit; and a second output transistor circuit for outputting an uninverted output logic signal based on a signal output by said differential output transistor circuit, wherein said differential output transistor circuit further comprises: first and second input units for inputting said two mutually complementary input logic signals; a first output unit connected to said first input unit; a second output unit connected to said second input unit; and first and second differential output units for outputting said output logic signals, said first output transistor circuit further comprises first and second field-effect transistors with the source of said first field-effect transistor connected to a positive power supply, the drain of said first field-effect transistor connected to the drain of said second field-effect transistor, the gate of said second field-effect transistor connected to said first output unit of said differential output transistor circuit and the gate of said first field-effect transistor connected to the source of said second field-effect transistor and said first differential output unit of said differential output transistor circuit, and said second output transistor circuit further comprises third and fourth field-effect transistors with the source of said third field-effect transistor connected to a positive power supply, the drain of said third field-effect transistor connected to the drain of said fourth field-effect transistor, the gate of said fourth field-effect transistor connected to said second output unit of said differential output transistor circuit and the gate of said third field-effect transistor connected to the source of said fourth field-effect transistor and said second differential output unit of said differential output transistor circuit.
Claim 2
Dependent Claim
306 words
A level converting circuit characterized by comprising: a differential output transistor circuit for amplifying a difference between two mutually complementary input logic signals; a first output transistor circuit for outputting an inverted output logic signal based on a signal output by said differential output transistor circuit; and a second output transistor circuit for outputting an uninverted output logic signal based on a signal output by said differential output transistor circuit, wherein said differential output transistor circuit further comprises: first and second input units for inputting said two mutually complementary input logic signals; a first output unit connected to said first input unit; a second output unit connected to said second input unit; and first and second differential output units for outputting said output logic signals, said first output transistor circuit further comprises first and second field-effect transistors with the source of said first field-effect transistor connected to a positive power supply, the drain of said first field-effect transistor connected to the drain of said second field-effect transistor, the gate of said second field-effect transistor connected to said first output unit of said differential output transistor circuit and the gate of said first field-effect transistor connected to the source of said second field-effect transistor and said first differential output unit of said differential output transistor circuit, and said second output transistor circuit further comprises third and fourth field-effect transistors with the source of said third field-effect transistor connected to a positive power supply, the drain of said third field-effect transistor connected to the drain of said fourth field-effect transistor, the gate of said fourth field-effect transistor connected to said second output unit of said differential output transistor circuit and the gate of said third field-effect transistor connected to the source of said fourth field-effect transistor and said second differential output unit of said differential output transistor circuit.
Claim 3
Dependent Claim
36 words
A level converting circuit according to claim 1 characterized in that said first and third field-effect transistors are each a p-type field-effect transistor and said second and fourth field-effect transistors are each an n-type field-effect transistor.
Claim 4
Dependent Claim
224 words
A level converting circuit according to claim 1 characterized in that: said differential output transistor circuit comprises first, second, third and fourth switching transistors, first, second, third, fourth and fifth bias components for setting a circuit constant and a constant-current supply; the drains of said first and third transistors are connected to one end of said first bias component, the source of said first transistor is connected to the drain of said second transistor, the source of said third transistor is connected to the drain of said fourth transistor, and the sources of said second and fourth transistors are connected to one end of said constant-current supply; said second and third bias components are connected in series between the source and the drain of said first transistor, the junction point of the series connection between said second and third bias components is connected to said first differential output unit, said fourth and fifth bias components are connected in series between the source and the drain of said third transistor, and the junction point of the series connection between said fourth and fifth bias components is connected to said second differential output unit; and the other end of said first bias component is connected to a positive power supply and said constant-current supply is connected to a positive power supply and a negative power supply.
Claim 5
Dependent Claim
31 words
A level converting circuit according to claim 3 characterized in that said first, second, third and fourth transistors and said constant-current supply is each made up of an n-type field-effect transistor.
Claim 6
Dependent Claim
29 words
A level converting circuit according to claim 3 characterized in that said first, second, third, fourth and fifth bias components are each a resistive element or a field-effect transistor.
Claim 7
Dependent Claim
19 words
A level converting circuit according to claim 3 characterized in that said first bias component is a field-effect transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-06-02 | 2000-12-02 | 2001-06-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-06-02 | 2004-12-02 | 2005-06-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-06-02 | 2008-12-02 | 2009-06-03 | $7700.00 | Window Closed / Lapsed |