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US5635736A
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MOS gate type semiconductor device
Assignee: Toshiba Corp
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Filing: 1995-09-13
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Granted: 1997-06-03
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Expires: 2015-09-13
Abstract
Abstract A MOS gate type semiconductor device, comprising an upper source wiring consisting of a plurality of upper source electrodes, an upper drain wiring provided on a semiconductor substrate and consisting of a plurality of upper drain electrodes formed in a comb-like arrangement such that the plurality of upper drain electrodes are engaged with the upper source electrodes, lower source electrodes provided at each of lower portions of adjacent pairs of the upper source electrodes and the upper drain electrodes such that the lower source electrodes are layered below the upper source electrodes and the upper drain electrodes, and lower drain electrodes provided at each of lower portions of adjacent pairs of the upper source electrodes and the upper drain electrodes electrode such that the lower drain electrodes are layered below the upper source electrodes and the upper drain electrodes, wherein the lower source electrodes are connected to the upper source electrodes and the source region, and are disposed so as to form a wave-like shape, and the lower drain electrodes are connected to the upper drain electrodes and the drain region, and are disposed so as to form a wave-like shape.
Inventors
- 👤 Hideyuki Funaki
- 👤 Yoshihiro Yamaguchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 13:21
CPC Classifications
H; H10; H10D; H10D48/00; H10D48/30; H10D48/32; H10D84/00; H10D84/201; H10D84/204; H10D84/209; H10D30/00; H10D30/60; H10D30/601; H10D30/603; H10D30/605; H10D62/00; H10D62/10; H10D62/124; H10D62/126; H10D64/00; H10D64/20; H10D64/23; H10D64/251; H10D64/256; H10D64/257; H10W; H10W20/00; H10W20/40; H10W20/482; H10W20/484
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
247 words
A MOS gate type semiconductor device, comprising: a semiconductor substrate on a surface of which a source region and a drain region are formed; an upper source wiring provided on the semiconductor substrate consisting of a plurality of upper source electrodes formed in a comb-like arrangement; an upper drain wiring provided on the semiconductor substrate consisting of a plurality of upper drain electrodes formed in a comb-like arrangement such that the plurality of upper drain electrodes are engaged with the upper source electrodes; lower source electrodes provided at each of lower portions of adjacent pairs of the upper source electrodes and the upper drain electrodes such that the lower source electrodes are layered below the upper source electrodes and the upper drain electrodes; and lower drain electrodes provided at each of lower portions of adjacent pairs of the upper source electrodes and the upper drain electrodes such that the lower drain electrodes are layered below the upper source electrodes and the upper drain electrodes, wherein the lower source electrodes are connected to the upper source electrodes and the source region, and are disposed so as to form a wave-like shape extending in a direction in which the upper source electrodes are disposed, and the lower drain electrodes are connected to the upper drain electrodes and the drain region, and are disposed so as to form a wave-like shape extending in a direction in which the upper drain electrodes are disposed, in parallel with the lower source electrodes.
Claim 2
Dependent Claim
247 words
A MOS gate type semiconductor device, comprising: a semiconductor substrate on a surface of which a source region and a drain region are formed; an upper source wiring provided on the semiconductor substrate consisting of a plurality of upper source electrodes formed in a comb-like arrangement; an upper drain wiring provided on the semiconductor substrate consisting of a plurality of upper drain electrodes formed in a comb-like arrangement such that the plurality of upper drain electrodes are engaged with the upper source electrodes; lower source electrodes provided at each of lower portions of adjacent pairs of the upper source electrodes and the upper drain electrodes such that the lower source electrodes are layered below the upper source electrodes and the upper drain electrodes; and lower drain electrodes provided at each of lower portions of adjacent pairs of the upper source electrodes and the upper drain electrodes such that the lower drain electrodes are layered below the upper source electrodes and the upper drain electrodes, wherein the lower source electrodes are connected to the upper source electrodes and the source region, and are disposed so as to form a wave-like shape extending in a direction in which the upper source electrodes are disposed, and the lower drain electrodes are connected to the upper drain electrodes and the drain region, and are disposed so as to form a wave-like shape extending in a direction in which the upper drain electrodes are disposed, in parallel with the lower source electrodes.
Claim 3
Dependent Claim
244 words
A MOS gate type semiconductor device, comprising: a semiconductor substrate on a surface of which a source region and a drain region are formed; an upper source wiring provided on the semiconductor substrate consisting of a plurality of upper source electrodes formed in a comb-like arrangement; an upper drain wiring provided on the semiconductor substrate and consisting of a plurality of upper drain electrodes formed in a comb-like arrangement such that the plurality of upper drain electrodes are engaged with the upper source electrodes; lower source electrodes provided at each of lower portions of adjacent pairs of the upper source electrodes and the upper drain electrodes such that the lower source electrodes are layered below the upper source electrodes and the upper drain electrodes; and lower drain electrodes provided at each of lower portions of adjacent pairs of the upper source electrodes and the upper drain electrodes such that the lower drain electrodes are layered below the upper source electrodes and the upper drain electrodes, wherein the lower source electrodes are connected to the upper source electrodes and the source region, and are disposed so as to form a wave-like shape extending in a lengthwise direction of the upper source electrodes, and the lower drain electrodes are connected to the upper drain electrodes and the drain region, and are disposed so as to form a wave-like shape extending in a lengthwise direction of the upper drain electrodes, in parallel with the lower source electrodes.
Claim 4
Dependent Claim
244 words
A MOS gate type semiconductor device, comprising: a semiconductor substrate on a surface of which a source region and a drain region are formed; an upper source wiring provided on the semiconductor substrate consisting of a plurality of upper source electrodes formed in a comb-like arrangement; an upper drain wiring provided on the semiconductor substrate and consisting of a plurality of upper drain electrodes formed in a comb-like arrangement such that the plurality of upper drain electrodes are engaged with the upper source electrodes; lower source electrodes provided at each of lower portions of adjacent pairs of the upper source electrodes and the upper drain electrodes such that the lower source electrodes are layered below the upper source electrodes and the upper drain electrodes; and lower drain electrodes provided at each of lower portions of adjacent pairs of the upper source electrodes and the upper drain electrodes such that the lower drain electrodes are layered below the upper source electrodes and the upper drain electrodes, wherein the lower source electrodes are connected to the upper source electrodes and the source region, and are disposed so as to form a wave-like shape extending in a lengthwise direction of the upper source electrodes, and the lower drain electrodes are connected to the upper drain electrodes and the drain region, and are disposed so as to form a wave-like shape extending in a lengthwise direction of the upper drain electrodes, in parallel with the lower source electrodes.
Claim 5
Dependent Claim
80 words
A MOS gate type semiconductor device, according to claim 1, wherein those of the lower source electrodes disposed to form the wave-like shape, which are connected to a same source region and are adjacent to each other, are formed to be integral with each other, and those of the lower drain electrodes disposed to form the wave-like shape, which are connected to a same drain region and are adjacent to each other, are formed to be integral with each other.
Claim 6
Dependent Claim
80 words
A MOS gate type semiconductor device, according to claim 2, wherein those of the lower source electrodes disposed to form the wave-like shape, which are connected to a same source region and are adjacent to each other, are formed to be integral with each other, and those of the lower drain electrodes disposed to form the wave-like shape, which are connected to a same drain region and are adjacent to each other, are formed to be integral with each other.
Claim 7
Dependent Claim
44 words
A MOS gate type semiconductor device, according to claim 1, wherein the lower source electrodes are disposed such that the lower source electrodes have a lengthwise direction oblique at an angle of 30° to 60° to a lengthwise direction of the upper source electrodes.
Claim 8
Dependent Claim
44 words
A MOS gate type semiconductor device, according to claim 2, wherein the lower source electrodes are disposed such that the lower source electrodes have a lengthwise direction oblique at an angle of 30° to 60° to a lengthwise direction of the upper source electrodes.
Claim 9
Dependent Claim
44 words
A MOS gate type semiconductor device, according to claim 1, wherein the lower drain electrodes are disposed such that the lower drain electrodes have a lengthwise direction oblique at an angle of 30° to 60° to a lengthwise direction of the upper drain electrodes.
Claim 10
Dependent Claim
44 words
A MOS gate type semiconductor device, according to claim 2, wherein the lower drain electrodes are disposed such that the lower drain electrodes have a lengthwise direction oblique at an angle of 30° to 60° to a lengthwise direction of the upper drain electrodes.
Claim 11
Dependent Claim
106 words
A MOS gate type semiconductor device, according to claim 1, wherein a contact area of a portion where one of the lower source electrodes is layered below one of the upper source electrodes is equal to a contact area of a portion where another one of the lower source electrodes is layered below another one of the upper source electrodes, and a contact area of a portion where one of the lower source electrodes is layered below one of the upper drain electrodes is equal to a contact area of a portion where one of the source electrodes is layered below one of the drain electrodes.
Claim 12
Dependent Claim
106 words
A MOS gate type semiconductor device, according to claim 2, wherein a contact area of a portion where one of the lower source electrodes is layered below one of the upper source electrodes is equal to a contact area of a portion where another one of the lower source electrodes is layered below another one of the upper source electrodes, and a contact area of a portion where one of the lower source electrodes is layered below one of the upper drain electrodes is equal to a contact area of a portion where one of the source electrodes is layered below one of the drain electrodes.
Claim 13
Dependent Claim
110 words
A MOS gate type semiconductor device, according to claim 1, wherein a contact area of a portion where one of the lower drain electrodes is layered below one of the upper drain electrodes is equal to a contact area of a portion where another one of the lower source electrodes is layered below another one of the upper source electrodes, and a contact area of a portion where one of the lower drain electrodes is layered below one of the upper source electrodes is equal to a contact area of a portion where another one of the lower drain electrodes is layered below another one of the upper source electrodes.
Claim 14
Dependent Claim
110 words
A MOS gate type semiconductor device, according to claim 2, wherein a contact area of a portion where one of the lower drain electrodes is layered below one of the upper drain electrodes is equal to a contact area of a portion where another one of the lower source electrodes is layered below another one of the upper source electrodes, and a contact area of a portion where one of the lower drain electrodes is layered below one of the upper source electrodes is equal to a contact area of a portion where another one of the lower drain electrodes is layered below another one of the upper source electrodes.
Claim 15
Dependent Claim
225 words
A MOS gate type semiconductor device, comprising: a semiconductor substrate on a surface of which a source region and a drain region are formed; an upper source wiring provided on the semiconductor substrate consisting of a plurality of upper source electrodes formed in a comb-like arrangement; an upper drain wiring provided on the semiconductor substrate consisting of a plurality of upper drain electrodes formed in a comb-like arrangement such that the plurality of upper drain electrodes are engaged with the upper source electrodes; lower source electrodes provided at each of lower portions of adjacent pairs of the upper source electrodes and the upper drain electrodes such that the lower source electrodes are layered below the upper source electrodes and the upper drain electrodes; and lower drain electrodes provided at each of lower portions of adjacent pairs of the upper source electrodes and the upper drain electrodes such that the lower drain electrodes are layered below the upper source electrodes and the upper drain electrodes, wherein the lower source electrodes are connected to the upper source electrodes and the source region, and have a lengthwise direction oblique to a lengthwise direction of the upper source electrodes, and the lower drain electrodes are connected to the upper drain electrodes and the drain region, and are formed to be disposed alternately in parallel with the lower source electrodes.
Claim 16
Dependent Claim
225 words
A MOS gate type semiconductor device, comprising: a semiconductor substrate on a surface of which a source region and a drain region are formed; an upper source wiring provided on the semiconductor substrate consisting of a plurality of upper source electrodes formed in a comb-like arrangement; an upper drain wiring provided on the semiconductor substrate consisting of a plurality of upper drain electrodes formed in a comb-like arrangement such that the plurality of upper drain electrodes are engaged with the upper source electrodes; lower source electrodes provided at each of lower portions of adjacent pairs of the upper source electrodes and the upper drain electrodes such that the lower source electrodes are layered below the upper source electrodes and the upper drain electrodes; and lower drain electrodes provided at each of lower portions of adjacent pairs of the upper source electrodes and the upper drain electrodes such that the lower drain electrodes are layered below the upper source electrodes and the upper drain electrodes, wherein the lower source electrodes are connected to the upper source electrodes and the source region, and have a lengthwise direction oblique to a lengthwise direction of the upper source electrodes, and the lower drain electrodes are connected to the upper drain electrodes and the drain region, and are formed to be disposed alternately in parallel with the lower source electrodes.
References Cited (Backward Citations)
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JPH01112749A
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EP0357410A2
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JPH04165678A
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JPH0513759A
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US5440154A
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2000-06-02 | 2000-12-02 | 2001-06-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-06-02 | 2004-12-02 | 2005-06-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-06-02 | 2008-12-02 | 2009-06-03 | $7700.00 | Window Closed / Lapsed |