EP0357410A2
Expired / Lapsed
EP
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Semiconductor integrated circuit device
Assignee: Kyushu Fujitsu Electronics Ltd
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Filing: 1989-08-31
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Granted: —
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Expires: 2009-08-31
Abstract
Abstract A semiconductor integrated circuit device comprises a pair of transistors (Qp,Qn) of the same conduction type having source regions (21,21′;23,23′) that are arranged adjacent to each other and facing each other, and a substrate contact diffusion region (31; 41) whose conduction type is opposite to that of the source regions (21,21′; 23,23′). The substrate contact diffusion region (31; 41) extends between the source regions (21, 21′; 23, 23′) Therefore, the source regions (21,21′; 23,23′) of the transistors (Qp,Qn) do not influence each other. This construction may be applied to a delay device having a plurality of inverter circuits connected in cascade.
Inventors
- 👤 Fumitaka Asami
- 👤 Shinya Udo
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 13:17
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/857; H10B; H10B20/00
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
84 words
A semiconductor integrated circuit device comprising a pair of transistors (Qp; Qn) of the same conduction type having source regions (21,21′; 23,23′) receiving a common power supply voltage (Vcc, Vss,) said source regions (21, 21′; 23, 23′) being arranged adjacent to each other and facing each other; and a substrate contact diffusion region (31; 41) whose conduction type is opposite to that of the source regions (21,21′; 23,23′), said substrate contact diffusion region (31; 41) extending between said source regions (21, 21′; 23, 23′).
Claim 2
Dependent Claim
84 words
A semiconductor integrated circuit device comprising a pair of transistors (Qp; Qn) of the same conduction type having source regions (21,21′; 23,23′) receiving a common power supply voltage (Vcc, Vss,) said source regions (21, 21′; 23, 23′) being arranged adjacent to each other and facing each other; and a substrate contact diffusion region (31; 41) whose conduction type is opposite to that of the source regions (21,21′; 23,23′), said substrate contact diffusion region (31; 41) extending between said source regions (21, 21′; 23, 23′).
Claim 3
Dependent Claim
30 words
A semiconductor integrated circuit device according to claim 1, wherein said substrate contact diffusion region (31; 41) has a higher impurity density than a well (12) or a substrate (11).
Claim 4
Dependent Claim
72 words
A semiconductor integrated circuit device according to claim 1 or 2, wherein said semiconductor integrated circuit device comprises plural stages of pairs of the same conduction type transistors (Qp; Qn), said substrate contact diffusion region (31; 34) extending to respective source regions (21,21′; 23,23′) of the pairs of transistors (Qp; Qn) in adjacent stages and protruding to approach channel forming regions of the transistors (Qp;Qn) having the respective source regions (21,21′; 23,23′).
Claim 5
Dependent Claim
133 words
A semiconductor integrated circuit device according to claim 3, wherein said semiconductor integrated circuit device comprises: a first power supply line (Vcc); a second power supply line (Vss); and a plurality of inverter circuits (I₁ , I₂ , I₃ , ...), being cascade-connected and each of said inverter circuits (I₁ , I₂, I₃, ...) being connected to said first and second power supply lines (Vcc, Vss), each of said inverter circuits (I₁ , I₂ , I₃ , ...) being constituted by a first conduction type transistor (Qp) and a second conduction type transistor (Qn), and said plural stage of pairs of said same conduction type transistors (Qp; Qn) being constituted by the first or second conduction type transistors (Qp; Qn) of said plurality of inverter circuits (I₁ , I₂ , I₃ , ...).
Claim 6
Dependent Claim
109 words
A semiconductor integrated circuit device according to claim 4, wherein said first conduction type transistor (Qp) is a P-channel type transistor and said second conduction type transistor (Qn) is an N-channel type transistor, and said first power supply line (Vcc) is used for applying a high potential power supply to a source region (21,21′) of each P-channel type transistor f(Qp) of said inverter circuits (I₁ , I₂ , I₃ , ...) and said second power supply line (Vss) is used for applying a low potential power supply to a source region (23,23′) of each N-channel type transistor (Qn) of said inverter circuits (I₁ , I₂ , I₃ , ...).
Claim 7
Dependent Claim
40 words
A semiconductor integrated circuit device according to any preceding claim, wherein said substrate contact diffusion region (131; 141) between the source regions (121,121′; 123,123′) of said pair of transistors (Qp; Qn) includes a contact portion (132′;142′) for connecting aluminum wiring.
Claim 8
Dependent Claim
42 words
A semiconductor integrated circuit device according to any preceding claim, wherein a distance of the substrate contact diffusion region (31; 41) between the source regions (21,21′; 23,23′) of said pair of transistors (Qp; Qn) is less than the minimum width of diffusion.
Claim 9
Dependent Claim
38 words
A semiconductor integrated circuit device according to claim 7, wherein the distance of the substrate contact diffusion region (31; 41) between the source regions (21,21′; 23,23′) of said pair of transistors (Qp; Qn) is less than 4 microns.
Claim 10
Dependent Claim
78 words
A semiconductor integrated circuit device according to claim 4 or 5, wherein source and drain regions (21,22; 23;24) of said first and second conduction type transistors (Qp; Qn) are arranged so that extensions of lines connecting the respective source and drain regions (21,22; 23,24) of said first and second conduction type transistors (Qp; Qn) intersect each other, and a conductive layer (51) having gate electrodes (51′,51˝) is disposed orthogonal to the source and drain regions (21,22; 23, 24).
Claim 11
Dependent Claim
41 words
A semiconductor integrated circuit device according to claim 9, wherein a plan shape of a wiring contact (61′,62′;63′,62˝) provided for each of the source and drain regions (21,22; 23,24) of said first and second conduction type transistors (Qp; Qn) is hexagonal.
Claim 12
Dependent Claim
56 words
A semiconductor integrated circuit device according to claim 9 or 10, wherein wiring (62) for connecting the drain regions (22,24) of said first and second conduction type transistors (Qp,Qn) with each other is curved opposite to a curve of the conductive layer (51) having the gate electrodes (51′,51˝) said first and second conduction type transistors (Qp,Qn).
Claim 13
Dependent Claim
59 words
A semiconductor integrated circuit device according to claim 9, 10, or 11, wherein a wiring (62) for connecting the drain regions (22,24) of said first and second conduction type transistors (Qp,Qn) with each other is connected to a conductive layer (51) having respective gate electrodes (51′,51˝) of a next stage inverter circuit (I₂ , I₃ , I₄ , ...).
Claim 14
Dependent Claim
63 words
A semiconductor integrated circuit device according to claim 9, 10, 11 or 12, wherein said plurality of inverter circuits (I₁, I₂, I₃,...) are arranged in plural rows (R₁ , R₂ , R₃ , ...), sequentially turned on even number of times and cascade-connected, the number of stages of the inverter circuits in each row (R₁ , R₂ , R₃ , ...) being odd.
Claim 15
Dependent Claim
24 words
A semiconductor integrated circuit device according to claim 13, wherein the number of stages of the inverter circuits in the last row is even.
Claim 16
Dependent Claim
33 words
A semiconductor integrated circuit device according to claim 13 ,or 14, wherein an ON resistance value of said first conduction type transistor (Qp) differs from that of said second conduction type transistor (Qn).
References Cited (Backward Citations)
No citation records indexed.
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