In-situ N2 plasma treatment for PE TEOS oxide deposition

Claim 1

A method of improving dielectric to dielectric adhesion in the manufacture of an integrated circuit comprising: providing semiconductor device structures in and on a semiconductor substrate; depositing a first dielectric layer overlying said semiconductor device structures and planarizing said first dielectric layer; depositing a conducting layer overlying said first dielectric layer and patterning said conducting layer wherein portions of said first dielectric layer are exposed; depositing a second dielectric layer overlying said patterned conducting layer and said exposed portions of said first dielectric layer wherein a simultaneous N 2 plasma treatment improves adhesion between said second dielectric layer and said exposed portions of said first dielectric layer; and completing the fabrication of said integrated circuit.

Claim 2

A method of improving dielectric to dielectric adhesion in the manufacture of an integrated circuit comprising: providing semiconductor device structures in and on a semiconductor substrate; depositing a first dielectric layer overlying said semiconductor device structures and planarizing said first dielectric layer; depositing a conducting layer overlying said first dielectric layer and patterning said conducting layer wherein portions of said first dielectric layer are exposed; depositing a second dielectric layer overlying said patterned conducting layer and said exposed portions of said first dielectric layer wherein a simultaneous N 2 plasma treatment improves adhesion between said second dielectric layer and said exposed portions of said first dielectric layer; and completing the fabrication of said integrated circuit.

Claim 13

A method of improving dielectric to dielectric adhesion in the manufacture of an integrated circuit comprising: providing semiconductor device structures in and on a semiconductor substrate; depositing a first dielectric layer overlying said semiconductor device structures and planarizing said first dielectric layer wherein said planarizing produces impurities on the surface of said first dielectric layer and wherein said impurities impede adhesion between said first dielectric layer and a second dielectric layer; depositing a conducting layer overlying said first dielectric layer and patterning said conducting layer wherein portions of said first dielectric layer are exposed; depositing said second dielectric layer overlying said patterned conducting layer and said exposed portions of said first dielectric layer wherein a simultaneous N 2 plasma treatment removes said impurities and consequently improves said adhesion between said second dielectric layer and said exposed portions of said first dielectric layer and wherein said second dielectric layer is deposited anisotropically whereby the thickness of said second dielectric layer is relatively greater on the horizontal surfaces of said patterned conducting layer and said exposed portions of said first dielectric layer than it is on the vertical surfaces of said patterned conducting layer; and completing the fabrication of said integrated circuit.

Claim 14

A method of improving dielectric to dielectric adhesion in the manufacture of an integrated circuit comprising: providing semiconductor device structures in and on a semiconductor substrate; depositing a first dielectric layer overlying said semiconductor device structures and planarizing said first dielectric layer wherein said planarizing produces impurities on the surface of said first dielectric layer and wherein said impurities impede adhesion between said first dielectric layer and a second dielectric layer; depositing a conducting layer overlying said first dielectric layer and patterning said conducting layer wherein portions of said first dielectric layer are exposed; depositing said second dielectric layer overlying said patterned conducting layer and said exposed portions of said first dielectric layer wherein a simultaneous N 2 plasma treatment removes said impurities and consequently improves said adhesion between said second dielectric layer and said exposed portions of said first dielectric layer and wherein said second dielectric layer is deposited anisotropically whereby the thickness of said second dielectric layer is relatively greater on the horizontal surfaces of said patterned conducting layer and said exposed portions of said first dielectric layer than it is on the vertical surfaces of said patterned conducting layer; and completing the fabrication of said integrated circuit.

Claim 22

A method of improving dielectric to dielectric adhesion in the manufacture of an integrated circuit comprising: providing semiconductor device structures in and on a semiconductor substrate; depositing a first dielectric layer overlying said semiconductor device structures and planarizing said first dielectric layer; depositing a conducting layer overlying said first dielectric layer and patterning said conducting layer wherein portions of said first dielectric layer are exposed; treating said exposed portions of said first dielectric layer with N 2 plasma thereby forming a depletion surface layer in said first dielectric layer wherein said treating with said N 2 plasma is performed at a temperature of between about 350° to 450° C.; thereafter depositing a second dielectric layer overlying said patterned conducting layer and said exposed portions of said first dielectric layer at a temperature of between about 350° to 450° C. wherein said temperature is 10° to 20° C. lower than previous said treating with said N 2 plasma and wherein said treating with said N 2 plasma and said depletion layer improve adhesion between said second dielectric layer and said exposed portions of said first dielectric layer; and completing the fabrication of said integrated circuit.

Claim 23

A method of improving dielectric to dielectric adhesion in the manufacture of an integrated circuit comprising: providing semiconductor device structures in and on a semiconductor substrate; depositing a first dielectric layer overlying said semiconductor device structures and planarizing said first dielectric layer; depositing a conducting layer overlying said first dielectric layer and patterning said conducting layer wherein portions of said first dielectric layer are exposed; treating said exposed portions of said first dielectric layer with N 2 plasma thereby forming a depletion surface layer in said first dielectric layer wherein said treating with said N 2 plasma is performed at a temperature of between about 350° to 450° C.; thereafter depositing a second dielectric layer overlying said patterned conducting layer and said exposed portions of said first dielectric layer at a temperature of between about 350° to 450° C. wherein said temperature is 10° to 20° C. lower than previous said treating with said N 2 plasma and wherein said treating with said N 2 plasma and said depletion layer improve adhesion between said second dielectric layer and said exposed portions of said first dielectric layer; and completing the fabrication of said integrated circuit.