Data transfer apparatus that compensates for differential signal delays

Claim 2

A data transfer apparatus for transferring data over a signal line to a plurality of data transfer destinations, comprising: clock generating means for generating and outputting a plurality of clocks having different phases with respect to each other; clock selecting means for receiving said plurality of clocks generated by said clock generating means, and for selecting one of said clocks for output therefrom; and data sending means for receiving the selected clock and for sending the data according to the selected clock to one of said plurality of data transfer destinations.

Claim 3

A data transfer apparatus as claimed in claim 1, wherein the clock selecting means selects one of said plurality of clocks generated by said clock generating means according to an address of said one of said plurality of data transfer destinations.

Claim 4

A data transfer apparatus as claimed in claim 2, wherein the phase of each of the plurality of clocks has a direct correspondence to one of the plurality of data transfer destinations, such that phase delays of the phases of the clocks correspond inverse proportionally to a physical distance between the data sending means and the data transfer destinations as indicated by the addresses of the data transfer destinations.

Claim 5

A data transfer apparatus as claimed in claim 3, wherein the time elapsing from clock selection by said clock selecting means to reception of data by said one of said plurality of data transfer destinations is constant regardless of data transfer destination.

Claim 6

A data transfer control apparatus for sending and receiving data over a signal line to and from a plurality of memory modules, said data transfer control apparatus comprising: first clock generating means for generating and outputting a first plurality of clocks having different phases with respect to each other; first clock selecting means for receiving said first plurality of clocks generated by said first clock generating means, and for selecting one of said first plurality of clocks for output therefrom, according to which data are to be written to a memory module; data sending means for receiving the selected clock and sending the data to be written according to the selected clock; second clock generating means for generating a second plurality of clocks having different phases with respect to each other; second clock selecting means for receiving said second plurality of clocks generated by said second clock generating means, and for selecting one of said second plurality of clocks, according to which data are to be read from a memory module; and data receiving means for receiving data read according to the clock selected by said second clock selecting means.

Claim 7

A data transfer control apparatus for sending and receiving data over a signal line to and from a plurality of memory modules, said data transfer control apparatus comprising: first clock generating means for generating and outputting a first plurality of clocks having different phases with respect to each other; first clock selecting means for receiving said first plurality of clocks generated by said first clock generating means, and for selecting one of said first plurality of clocks for output therefrom, according to which data are to be written to a memory module; data sending means for receiving the selected clock and sending the data to be written according to the selected clock; second clock generating means for generating a second plurality of clocks having different phases with respect to each other; second clock selecting means for receiving said second plurality of clocks generated by said second clock generating means, and for selecting one of said second plurality of clocks, according to which data are to be read from a memory module; and data receiving means for receiving data read according to the clock selected by said second clock selecting means.

Claim 8

A data transfer control apparatus as defined in claim 5, wherein each of said plurality of memory modules includes a circuit for receiving the data to be written and a circuit for sending the read data, and wherein all of said circuits for receiving the data to be written and all of said circuits for sending the read data operate on a common clock.

Claim 9

A data transfer control apparatus according to claim 5, wherein said first clock selecting means selects one of said first plurality of clocks generated by said first clock generating means according to an address of the memory module to which data are to be written; and wherein said second clock selecting means selects one of said second plurality of clocks generated by said second clock generating means according to an address of the memory module from which data are to be read.

Claim 10

A data transfer control apparatus as claimed in claim 7, wherein the phase of each of the first plurality of clocks generated by said first clock generating means has a direct correspondence to one of the memory modules to which data are to be written; and wherein said first clock selecting means selects one of said first plurality of clocks generated by said first clock generating means according to an address of the memory module to which data are to be written; such that phase delays of the clocks generated by the first and second clock generating means correspond inverse-proportionally to physical distance between the data sending means and the memory modules to which data are to be written, and between the memory modules from which data are to be read and the data receiving means, respectively.

Claim 11

A data transfer control apparatus as claimed in claim 8, wherein the time elapsing from clock selection by said first clock selecting means to reception of data by any of said memory modules to which data are to be written is constant regardless of memory module.

Claim 12

A data transfer system in which a plurality of units are connected with each other by a bus line for transferring data, each unit sending and receiving data from another unit by said bus line, said plurality of units each comprising: clock generating means for generating and outputting a plurality of clocks having different phases; clock selecting means for receiving said plurality of clocks generated by said clock generating means, and for selecting one of said plurality of clocks for output therefrom; and data sending means for sending data according to the clock selected by said clock selecting means to a receiving unit of said plurality of units other than the unit sending the data.

Claim 13

A data transfer system in which a plurality of units are connected with each other by a bus line for transferring data, each unit sending and receiving data from another unit by said bus line, said plurality of units each comprising: clock generating means for generating and outputting a plurality of clocks having different phases; clock selecting means for receiving said plurality of clocks generated by said clock generating means, and for selecting one of said plurality of clocks for output therefrom; and data sending means for sending data according to the clock selected by said clock selecting means to a receiving unit of said plurality of units other than the unit sending the data.

Claim 14

A data transfer system according to claim 10, wherein said clock selecting means selects one of said plurality of clocks generated by said clock generating means according to an address of the unit sending the data and an address of the receiving unit.

Claim 15

A data transfer system as claimed in claim 11, wherein the phase of each of the plurality of clocks generated by said clock generating means has a direct correspondence to one of the plurality of units other than the unit generating the clock, such that phase delays of the phases of the clocks correspond inverse-proportionally to physical distances between the data sending means and each of the plurality of units other than the unit sending the data.

Claim 16

A data transfer system as claimed in claim 12, wherein time elapsing from clock selection by said clock selecting means to reception of data by said receiving unit is constant regardless of receiving unit.

Claim 17

A data transfer system as claimed in claim 11, wherein each unit further includes data receiving means for receiving data sent by data sending means from a unit other than the unit receiving the data.

Claim 18

A data transfer apparatus for sending and receiving data over a signal line, comprising: a send clock determining circuit for receiving information representing an address to which send data are to be transmitted by the data transfer apparatus, and for determining a clock timing according to which the send data are to be transmitted by the data transfer apparatus based on the received information; a receive clock determining circuit for receiving information representing an address from which receive data are to be received by the data transfer apparatus, and for determining a clock timing according to which the receive data are to be received by the data transfer apparatus based on the received information; and a controller for receiving an external processing request and for providing an enable signal to one of the send clock determining circuit and the receive clock determining circuit in response to the external processing request.

Claim 19

A data transfer apparatus for sending and receiving data over a signal line, comprising: a send clock determining circuit for receiving information representing an address to which send data are to be transmitted by the data transfer apparatus, and for determining a clock timing according to which the send data are to be transmitted by the data transfer apparatus based on the received information; a receive clock determining circuit for receiving information representing an address from which receive data are to be received by the data transfer apparatus, and for determining a clock timing according to which the receive data are to be received by the data transfer apparatus based on the received information; and a controller for receiving an external processing request and for providing an enable signal to one of the send clock determining circuit and the receive clock determining circuit in response to the external processing request.

Claim 20

A data transfer apparatus according to claim 15, further comprising: a first clock generating circuit for generating and outputting a first plurality of clocks having different phases with respect to each other, wherein said send clock determining circuit selects one of said first plurality of clocks generated by said first clock generating circuit according to the information representing the address to which the send data are to be transmitted; and a second clock generating circuit for generating a second plurality of clocks having different phases with respect to each other, wherein said receive clock determining circuit selects one of said second plurality of clock generated by said second clock generating circuit according to the information representing the address from which the receive data are to be received.

Claim 21

A data transfer apparatus as claimed in claim 16, wherein the time elapsing from clock selection by said send clock determining circuit to reception of data by any destination of said transmitted data is constant regardless of destination.

Claim 22

A data transfer apparatus for transferring data over a signal line to a plurality of data transfer destinations, comprising: a clock generator having an output of a plurality of clocks having different phases with respect to each other; a clock selector having inputs that receive said plurality of clocks generated by said clock generator means, that selects one of said clocks for output therefrom; and a data sending circuit having an input that receives the selected clock, that sends the data according to the selected clock to one of said plurality of data transfer destinations.

Claim 23

A data transfer apparatus for transferring data over a signal line to a plurality of data transfer destinations, comprising: a clock generator having an output of a plurality of clocks having different phases with respect to each other; a clock selector having inputs that receive said plurality of clocks generated by said clock generator means, that selects one of said clocks for output therefrom; and a data sending circuit having an input that receives the selected clock, that sends the data according to the selected clock to one of said plurality of data transfer destinations.

Claim 24

A data transfer system in which a plurality of units are connected with each other by a bus line for transferring data, each unit sending and receiving data from another unit by said bus line, said plurality of units each comprising: a clock generator having an output of a plurality of clocks having different respective phases; a clock selector having inputs that receive said plurality of clocks generated by said clock generator means, that selects one of said clocks for output therefrom; and a data sending circuit having an input that receives the clock selected by said clock selector, that sends the data to a receiving unit of said plurality of units other than the unit sending the data.

Claim 25

A data transfer system in which a plurality of units are connected with each other by a bus line for transferring data, each unit sending and receiving data from another unit by said bus line, said plurality of units each comprising: a clock generator having an output of a plurality of clocks having different respective phases; a clock selector having inputs that receive said plurality of clocks generated by said clock generator means, that selects one of said clocks for output therefrom; and a data sending circuit having an input that receives the clock selected by said clock selector, that sends the data to a receiving unit of said plurality of units other than the unit sending the data.

Claim 26

A data transfer system according to claim 19, wherein said clock selector selects one of said plurality of clocks according to an address of the unit sending the data and an address of the receiving unit.

Claim 27

A data transfer system as claimed in claim 20, wherein the phase of each of the plurality of clocks generated by said clock generator has a direct correspondence to one of the plurality of units other than the unit generating the clock, such that phase delays of the phases of the clocks correspond inverse-proportionally to physical distances between the data sending circuit and each of the plurality of units other than the unit sending the data.

Claim 28

A data transfer system as claimed in claim 21, wherein time elapsing from clock selection by said clock selector to reception of data by said receiving unit is constant regardless of receiving unit.

Claim 29

A data transfer system as claimed in claim 20, wherein each unit further includes a data receiving circuit having an input that receives data sent by a data sending circuit from a unit other than the unit receiving the data.