US5633607A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Edge triggered set-reset flip-flop (SRFF)
Assignee: Mosaid Technologies Inc
•
Filing: 1995-04-28
•
Granted: 1997-05-27
•
Expires: 2015-04-28
Abstract
Abstract A timer comprised of first and second gated SR (set-reset) latches each including two pair (S1, S2 and R1, R2) of inputs and a pair of outputs (Q, QN), the Q output of the first latch being connected to the R2 input of the second latch, and the QN output of the first latch being connected to the S2 input of the second latch, the Q output of the second latch being connected to the S2 input of the first latch, and the QN output of the second latch being connected to the R2 input of the first latch, apparatus for applying a delayed representation of a first pulse signal to the S1 input of the first latch and apparatus for applying a delayed representation of a second pulse signal to the R1 input of the first latch, apparatus for applying an inverted representation of the pulse signal to the S1 input of the second latch and apparatus for applying an inverted representation of the second pulse signal to the R1 input of the second latch, whereby timed output signals representing a differential between leading edges of the first and second pulse signals are provided at the outputs Q, QN of the second latch.
Inventors
- 👤 Bruce Millar
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 15:47
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/037; H03K23/00; H03K23/58; H03K5/00; H03K5/153; H03K5/1534
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
234 words
A timer comprising: (a) first and second gated SR (set-reset) latches each including two pair of inputs S1, S2 and R1, R2 and a pair of outputs Q, QN, (b) the Q output of the first gated SR latch being connected to the R2 input of the second gated SR latch, and the QN output of the first gated SR latch being connected to the S2 input of the second gated SR latch, (c) the Q output of the second gated SR latch being connected to the S2 input of the first gated SR latch, and the QN output of the second gated SR latch being connected to the R2 input of the first gated SR latch, (d) means for applying a delayed representation of a first pulse signal to the S1 input of the first gated SR latch and means for applying a delayed representation of a second pulse signal to the R1 input of the first gated SR latch, (e) means for applying an inverted representation of the first pulse signal to the S1 input of the second gated SR latch and means for applying an inverted representation of the second pulse signal to the R1 input of the second gated SR latch, whereby output signals representing a differential between leading edges of the first and second pulse signals are provided at the outputs Q, QN of the second gated SR latch.
Claim 2
Dependent Claim
234 words
A timer comprising: (a) first and second gated SR (set-reset) latches each including two pair of inputs S1, S2 and R1, R2 and a pair of outputs Q, QN, (b) the Q output of the first gated SR latch being connected to the R2 input of the second gated SR latch, and the QN output of the first gated SR latch being connected to the S2 input of the second gated SR latch, (c) the Q output of the second gated SR latch being connected to the S2 input of the first gated SR latch, and the QN output of the second gated SR latch being connected to the R2 input of the first gated SR latch, (d) means for applying a delayed representation of a first pulse signal to the S1 input of the first gated SR latch and means for applying a delayed representation of a second pulse signal to the R1 input of the first gated SR latch, (e) means for applying an inverted representation of the first pulse signal to the S1 input of the second gated SR latch and means for applying an inverted representation of the second pulse signal to the R1 input of the second gated SR latch, whereby output signals representing a differential between leading edges of the first and second pulse signals are provided at the outputs Q, QN of the second gated SR latch.
Claim 3
Dependent Claim
31 words
A timer as defined in claim 1 in which each of the means for applying inverted and delayed representations of the first and second pulse signals is comprised of an inverter.
Claim 4
Dependent Claim
100 words
A timer as defined in claim 1 in which each of the first and second gated SR latches has set and reset inputs SD and RD, the SD inputs being connected together and the RD inputs being connected together, each of the first and second gated SR latches being comprised of a pair of logic circuits each having a Boolean transfer function /Z=(A+B)CD where /Z represents the logic level at an output Q or QN, A and B represent pairs of inputs S1, S2 or R1, R2 and C and D represent directly set input logic levels SD or RD.
Claim 5
Dependent Claim
105 words
A ripple counter comprising a plurality of timers each as defined in claim 3, a clock source being connected to both inputs together of a first timer of said plurality of timers, means for applying a direct set logic signal to the SD inputs of all the timers together, means for applying a direct reset logic signal to the RD inputs of all the timers together, the QN output of each of the timers except a last timer being connected to both inputs together of a following timer, and means for providing a count output signal from the Q output of each of the timers.
Claim 6
Dependent Claim
92 words
A pulse generator comprising a pair of delay lines having different delays, means for applying a clock signal to an input of both of the delay lines, a timer as defined in claim 3, outputs of the delay lines being connected to respective inputs of the timer, means for applying a high logic level signal to the SD input of the timer and means for applying a direct reset signal to the RD input of the timer, and means for providing a pulse output signal from the Q output of the timer.
Claim 7
Dependent Claim
137 words
A rising edge detector comprising a timer as defined in claim 3, a D-type flip-flop, means for applying an input signal to one input of the timer, the Q output of the timer being connected to a D input of the flip flop, means for applying a clock signal to the other input of the timer and to a clock input of the flip flop, means for applying a high logic level signal to the SD input of the timer and to a preset input of the flip flop, means for applying a reset signal to the RD input of the timer and to a clear input of the flip flop, and means for providing an output signal representing detection of a rising edge of the input signal at a Q output of the D-type flip flop.
References Cited (Backward Citations)
US3509381A
Cited
US3882325A
Cited
US4300060A
Cited
US4394769A
Cited
EP0098203A1
Cited
US4568843A
Cited
US5065052A
Cited
US5059818A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-05-26 | 2000-11-25 | 2001-05-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-05-26 | 2004-11-25 | 2005-05-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-05-26 | 2008-11-25 | 2009-05-27 | $7700.00 | Window Closed / Lapsed |