Patent US5633532A successfully refreshed from Google Patents.
US5633532A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device interconnection
Assignee: Socionext Inc
•
Filing: 1995-04-21
•
Granted: 1997-05-27
•
Expires: 2015-04-21
Abstract
Abstract A semiconductor apparatus includes a semiconductor element and a substrate having a substrate base and a thin-film multilayer interconnection layer formed on the substrate base. The thin-film multilayer interconnection layer has insulating layers and interconnection patterns. The insulating layers and the interconnection patterns are alternately layered. Each of the insulating layers includes a first insulating layer part and a second insulating layer part. A surface of the second insulating layer part is more flat than that of the first insulating layer part, and each of the interconnection patterns is arranged on the surface of the second insulating layer part.
Inventors
- 👤 Tuyosi Sohara
- 👤 Hirohisa Matsuki
- 👤 Toshiyuki Kuramochi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 08:06
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/60; H10W70/67; H10W70/69; H05; H05K; H05K1/00; H05K1/02; H05K1/11; H05K1/115; H05K1/16; H05K1/162; H10W40/00; H10W40/70; H10W40/77; H10W44/00; H10W44/601; H10W70/611; H10W70/62; H10W70/63; H10W70/635; H05K2201/00; H05K2201/09; H05K2201/09209; H05K2201/09218; H05K2201/09236; H05K2201/095; H05K2201/09509; H05K2201/09627; H05K3/00; H05K3/46; H05K3/4644; H05K3/4673; H05K3/4676; H10W72/00; H10W72/50; H10W72/531; H10W72/536; H10W90/00; H10W90/701; H10W90/721; H10W90/724
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
136 words
A semiconductor apparatus comprising: a semiconductor element; and a substrate having a substrate base and a thin-film multilayer interconnection layer formed on the substrate base, said thin-film multilayer interconnection layer having: insulating layers; and interconnection patterns, said insulating layers and said interconnection patterns being alternately layered; wherein each of said insulating layers comprises: a first insulating layer part substantially covering said interconnection pattern; and a second insulating layer part provided directly on the first insulating layer part to substantially cover the first insulating layer part; wherein said thin-film multilayer interconnection layer is in the absence of an empty space; and a surface of the second insulating layer part is more flat than that of the first insulating layer part, and each of said interconnection patterns is arranged on the surface of said second insulating layer part.
Claim 2
Dependent Claim
136 words
A semiconductor apparatus comprising: a semiconductor element; and a substrate having a substrate base and a thin-film multilayer interconnection layer formed on the substrate base, said thin-film multilayer interconnection layer having: insulating layers; and interconnection patterns, said insulating layers and said interconnection patterns being alternately layered; wherein each of said insulating layers comprises: a first insulating layer part substantially covering said interconnection pattern; and a second insulating layer part provided directly on the first insulating layer part to substantially cover the first insulating layer part; wherein said thin-film multilayer interconnection layer is in the absence of an empty space; and a surface of the second insulating layer part is more flat than that of the first insulating layer part, and each of said interconnection patterns is arranged on the surface of said second insulating layer part.
Claim 3
Dependent Claim
43 words
The semiconductor apparatus as claimed in claim 1, wherein said first insulating layer part is made of blended resin with which an additive is blended, and said second insulating layer part is made of an insulating material with which no additive is blended.
Claim 4
Dependent Claim
25 words
The semiconductor apparatus as claimed in claim 1, wherein said second insulating layer part has a thinner thickness than that of said first insulating layer.
Claim 5
Dependent Claim
33 words
The semiconductor apparatus as claimed in claim 1, wherein said first insulating layer part is made of at least one of materials of benzocyclobutene (BCB), polyimide resin, epoxy resin, and spin-on glass (SOG).
Claim 6
Dependent Claim
134 words
A semiconductor apparatus comprising: a semiconductor element; and a substrate having a substrate base and a thin-film multilayer interconnection layer formed on the substrate base, said thin-film multilayer interconnection layer having: insulating layers; interconnection patterns; and a via structure section, said insulating layers and said interconnection patterns being alternately layered; wherein said via structure section comprises: a plurality of pads which are alternately layered with said insulating layers, each of said pads including a plurality of arm parts extending in a radial manner outwardly, wherein said arm parts of said pads are arranged so as to overlap each other through said insulating layers; and vias, formed in said insulating layers, electrically being directly connected to said arm parts of the pads together, wherein said vias are arranged so as not to overlap each other.
Claim 7
Dependent Claim
134 words
A semiconductor apparatus comprising: a semiconductor element; and a substrate having a substrate base and a thin-film multilayer interconnection layer formed on the substrate base, said thin-film multilayer interconnection layer having: insulating layers; interconnection patterns; and a via structure section, said insulating layers and said interconnection patterns being alternately layered; wherein said via structure section comprises: a plurality of pads which are alternately layered with said insulating layers, each of said pads including a plurality of arm parts extending in a radial manner outwardly, wherein said arm parts of said pads are arranged so as to overlap each other through said insulating layers; and vias, formed in said insulating layers, electrically being directly connected to said arm parts of the pads together, wherein said vias are arranged so as not to overlap each other.
Claim 8
Dependent Claim
88 words
A semiconductor apparatus comprising: a semiconductor element, and a substrate having a substrate base and a thin-film multilayer interconnection layer formed on the substrate base, said thin-film multilayer interconnection layer having: insulating layers; interconnection patterns: and a decoupling capacitance, said insulating layers and said interconnection patterns being alternately layered; wherein said decoupling capacitance comprises: a pair of interdigital electrodes respectively including tooth parts which are alternately arranged, and a dielectric part filling a gap between adjoining tooth parts; wherein a value of the decoupling capacitance may relatively increase.
Claim 9
Dependent Claim
88 words
A semiconductor apparatus comprising: a semiconductor element, and a substrate having a substrate base and a thin-film multilayer interconnection layer formed on the substrate base, said thin-film multilayer interconnection layer having: insulating layers; interconnection patterns: and a decoupling capacitance, said insulating layers and said interconnection patterns being alternately layered; wherein said decoupling capacitance comprises: a pair of interdigital electrodes respectively including tooth parts which are alternately arranged, and a dielectric part filling a gap between adjoining tooth parts; wherein a value of the decoupling capacitance may relatively increase.
Claim 10
Dependent Claim
22 words
The semiconductor apparatus as claimed in claim 6, wherein each of said interdigital electrodes comprises a tooth part of a bending form.
Claim 11
Dependent Claim
24 words
The semiconductor apparatus as claimed in claim 6, wherein each of said interdigital electrodes has a thinner thickness than that of said decoupling capacitance.
References Cited (Backward Citations)
US5338975A
Cited
JPH0481879A
Cited
JPH0481878A
Cited
WO1992006496A1
Cited
JPH0587977A
Cited
US5410107A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-05-26 | 2000-11-25 | 2001-05-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-05-26 | 2004-11-25 | 2005-05-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-05-26 | 2008-11-25 | 2009-05-27 | $7700.00 | Window Closed / Lapsed |