Non-volatile floating gate semiconductor device

Claim 2

A semiconductor device comprising: a semiconductor substrate having a lower surface and a protrusion extending from the lower surface, said protrusion having a side surface; a first impurity region formed in an upper portion of said protrusion; a second impurity region formed within said lower surface of the semiconductor substrate adjacent to said protrusion; a floating gate electrode adjacent to said side surface of the protrusion, said floating gate electrode being insulated from said protrusion by a first insulating layer interposed therebetween, said floating gate electrode and said first insulating layer extending from said first impurity region to and not beyond an intermediate portion of said side surface of the protrusion, said intermediate portion of the side surface being disposed between the lower surface of the semiconductor substrate and the upper portion of the protrusion; and a gate electrode formed adjacent to said floating gate electrode with a second insulating layer therebetween, said gate electrode extending beyond a lower edge of said floating gate electrode between said first and second impurity regions.

Claim 3

The semiconductor device of claim 1 wherein said semiconductor substrate comprises a single crystalline silicon.

Claim 4

The semiconductor device of claim 2 wherein said side surface has a crystal orientation (100).

Claim 5

The semiconductor device of claim 1 wherein said first insulating layer comprises silicon oxide.

Claim 6

The semiconductor device of claim 1 wherein said first insulating layer is 10-500 nm thick.

Claim 7

The semiconductor device of claim 1 wherein said first impurity region is 10-500 nm thick.

Claim 8

A semiconductor device comprising: a semiconductor substrate having a lower surface and a protrusion extending from the lower surface, said protrusion having a side surface; a first impurity region formed in an upper portion of said protrusion; a second impurity region formed within said lower surface of the semiconductor substrate adjacent to said protrusion; a floating gate electrode adjacent to said side surface of the protrusion, said floating gate electrode being insulated from said protrusion by a first insulating layer interposed therebetween; and a gate electrode formed adjacent to said floating gate electrode with a second insulating layer therebetween, wherein said first insulating layer has a portion adjacent to said first impurity region selectively thinned.

Claim 9

A semiconductor device comprising: a semiconductor substrate having a lower surface and a protrusion extending from the lower surface, said protrusion having a side surface; a first impurity region formed in an upper portion of said protrusion; a second impurity region formed within said lower surface of the semiconductor substrate adjacent to said protrusion; a floating gate electrode adjacent to said side surface of the protrusion, said floating gate electrode being insulated from said protrusion by a first insulating layer interposed therebetween; and a gate electrode formed adjacent to said floating gate electrode with a second insulating layer therebetween, wherein said first insulating layer has a portion adjacent to said first impurity region selectively thinned.

Claim 10

The semiconductor device of claim 7 wherein said semiconductor substrate comprises a single crystalline silicon.

Claim 11

The semiconductor device of claim 8 wherein said side surface has a crystal orientation (100).

Claim 12

The semiconductor device of claim 7 wherein said first insulating layer comprises silicon oxide.

Claim 13

The semiconductor device of claim 7 wherein said first insulating layer is 10-500 nm thick.

Claim 14

The semiconductor device of claim 7 wherein said first impurity region is 10-500 nm thick.

Claim 15

A semiconductor device comprising: a semiconductor substrate having a lower surface and a protrusion extending from the lower surface, said protrusion having a side surface; a first impurity region formed in an upper portion of said protrusion; a second impurity region formed within said lower surface of the semiconductor substrate adjacent to said protrusion; a floating gate electrode adjacent to said side surface of the protrusion, said floating gate electrode being insulated from said protrusion by a first insulating layer interposed therebetween; and a gate electrode formed adjacent to said floating gate electrode with a second insulating layer therebetween, wherein said first impurity region comprises a first layer having a first impurity concentration, a second layer having a second impurity concentration located on said first layer and a third layer having a third impurity concentration located on said second layer, said second impurity concentration being higher than said first and third impurity concentrations.

Claim 16

A semiconductor device comprising: a semiconductor substrate having a lower surface and a protrusion extending from the lower surface, said protrusion having a side surface; a first impurity region formed in an upper portion of said protrusion; a second impurity region formed within said lower surface of the semiconductor substrate adjacent to said protrusion; a floating gate electrode adjacent to said side surface of the protrusion, said floating gate electrode being insulated from said protrusion by a first insulating layer interposed therebetween; and a gate electrode formed adjacent to said floating gate electrode with a second insulating layer therebetween, wherein said first impurity region comprises a first layer having a first impurity concentration, a second layer having a second impurity concentration located on said first layer and a third layer having a third impurity concentration located on said second layer, said second impurity concentration being higher than said first and third impurity concentrations.

Claim 17

The semiconductor device of claim 13 wherein said semiconductor substrate comprises a single crystalline silicon.

Claim 18

The semiconductor device of claim 14 wherein said side surface has a crystal orientation (100).

Claim 19

The semiconductor device of claim 13 wherein said first insulating layer comprises silicon oxide.

Claim 20

The semiconductor device of claim 13 wherein said first insulating layer is 10-500 nm thick.

Claim 21

A semiconductor memory device comprising: (1) a semiconductor substrate having a lower surface; (2) a plurality of memory elements arranged in column and row directions, each of said memory elements comprising: a semiconductor protrusion extending from the lower surface of said substrate, said protrusion having a side surface; a first impurity region formed in an upper portion of said protrusion; a second impurity region formed within said lower surface of the semiconductor substrate adjacent to said protrusion, wherein said second impurity region does not extend below said protrusion; a floating gate electrode adjacent to said side surface of the protrusion, said floating gate electrode being insulated from said protrusion by a first insulating layer therebetween; and a gate electrode formed adjacent to said floating gate electrode with a second insulating layer therebetween; (3) a plurality of gate lines extending in the column direction connected to the gate electrode of the memory elements arranged in the column direction, respectively; (4) a plurality of bit lines extending in the row direction and connected to the first impurity region of the memory elements arranged in the row direction, respectively; and (5) an interlayer insulator formed over said semiconductor substrate with said bit lines overlaying thereon, wherein said bit lines contact the first impurity region of the memory elements on an upper most surface of the respective protrusions through contact holes formed in said interlayer insulator.

Claim 22

A semiconductor memory device comprising: (1) a semiconductor substrate having a lower surface; (2) a plurality of memory elements arranged in column and row directions, each of said memory elements comprising: a semiconductor protrusion extending from the lower surface of said substrate, said protrusion having a side surface; a first impurity region formed in an upper portion of said protrusion; a second impurity region formed within said lower surface of the semiconductor substrate adjacent to said protrusion, wherein said second impurity region does not extend below said protrusion; a floating gate electrode adjacent to said side surface of the protrusion, said floating gate electrode being insulated from said protrusion by a first insulating layer therebetween; and a gate electrode formed adjacent to said floating gate electrode with a second insulating layer therebetween; (3) a plurality of gate lines extending in the column direction connected to the gate electrode of the memory elements arranged in the column direction, respectively; (4) a plurality of bit lines extending in the row direction and connected to the first impurity region of the memory elements arranged in the row direction, respectively; and (5) an interlayer insulator formed over said semiconductor substrate with said bit lines overlaying thereon, wherein said bit lines contact the first impurity region of the memory elements on an upper most surface of the respective protrusions through contact holes formed in said interlayer insulator.

Claim 23

A semiconductor memory device comprising: (1) a semiconductor substrate having a lower surface; (2) a plurality of memory elements arranged in column and row directions, each of said memory elements comprising: a semiconductor protrusion extending from the lower surface of said substrate, said protrusion having a side surface; a first impurity region formed in an upper portion of said protrusion; a second impurity region formed within said lower surface of the semiconductor substrate adjacent to said protrusion; a floating gate electrode adjacent to said side surface of the protrusion, said floating gate electrode being insulated from said protrusion by a first insulating layer therebetween; and a gate electrode formed adjacent to said floating gate electrode with a second insulating layer therebetween; (3) a plurality of gate lines extending in the column direction and connected to the gate electrode of the memory elements arranged in the column direction, respectively; (4) a plurality of source lines mainly extending in the column direction and connected to the second impurity region of the memory elements arranged in the column direction, respectively; (5) a plurality of bit lines extending in the row direction and connected to the first impurity region of the memory elements arranged in the row direction, respectively; and (6) an interlayer insulator formed over said semiconductor substrate with said bit lines overlaying thereon, wherein said bit lines contact the first impurity region of the memory elements on an upper most surface of the respective protrusions through contact holes formed in said interlayer insulator.

Claim 24

A semiconductor memory device comprising: (1) a semiconductor substrate having a lower surface; (2) a plurality of memory elements arranged in column and row directions, each of said memory elements comprising: a semiconductor protrusion extending from the lower surface of said substrate, said protrusion having a side surface; a first impurity region formed in an upper portion of said protrusion; a second impurity region formed within said lower surface of the semiconductor substrate adjacent to said protrusion; a floating gate electrode adjacent to said side surface of the protrusion, said floating gate electrode being insulated from said protrusion by a first insulating layer therebetween; and a gate electrode formed adjacent to said floating gate electrode with a second insulating layer therebetween; (3) a plurality of gate lines extending in the column direction and connected to the gate electrode of the memory elements arranged in the column direction, respectively; (4) a plurality of source lines mainly extending in the column direction and connected to the second impurity region of the memory elements arranged in the column direction, respectively; (5) a plurality of bit lines extending in the row direction and connected to the first impurity region of the memory elements arranged in the row direction, respectively; and (6) an interlayer insulator formed over said semiconductor substrate with said bit lines overlaying thereon, wherein said bit lines contact the first impurity region of the memory elements on an upper most surface of the respective protrusions through contact holes formed in said interlayer insulator.

Claim 25

A semiconductor memory device comprising: (1) a semiconductor substrate having a lower surface; (2) a plurality of memory elements arranged in column and row directions, each of said memory elements comprising: a semiconductor protrusion extending from the lower surface of said substrate, said protrusion having a side surface; a first impurity region formed in an upper portion of said protrusion; a second impurity region formed within said lower surface of the semiconductor substrate adjacent to said protrusion, wherein said second impurity region does not extend below said protrusion; a floating gate electrode adjacent to said side surface of the protrusion, said floating gate electrode being insulated from said protrusion by a first insulating layer therebetween; and a gate electrode formed adjacent to said floating gate electrode with a second insulating layer therebetween; and (3) a plurality of bit lines extending in the row direction and connected to the first impurity region of the memory elements arranged in the row direction, respectively, wherein each of the memory elements is isolated from adjacent one of the memory elements arranged in the column direction by an oxide insulator.

Claim 26

A semiconductor memory device comprising: (1) a semiconductor substrate having a lower surface; (2) a plurality of memory elements arranged in column and row directions, each of said memory elements comprising: a semiconductor protrusion extending from the lower surface of said substrate, said protrusion having a side surface; a first impurity region formed in an upper portion of said protrusion; a second impurity region formed within said lower surface of the semiconductor substrate adjacent to said protrusion, wherein said second impurity region does not extend below said protrusion; a floating gate electrode adjacent to said side surface of the protrusion, said floating gate electrode being insulated from said protrusion by a first insulating layer therebetween; and a gate electrode formed adjacent to said floating gate electrode with a second insulating layer therebetween; and (3) a plurality of bit lines extending in the row direction and connected to the first impurity region of the memory elements arranged in the row direction, respectively, wherein each of the memory elements is isolated from adjacent one of the memory elements arranged in the column direction by an oxide insulator.

Claim 27

The semiconductor memory device of claim 20 wherein said oxide insulator is a LOCOS.

Claim 28

A semiconductor device comprising: (1) a semiconductor substrate having a lower surface; (2) a memory circuit comprising a plurality of semiconductor memory elements, each of the semiconductor memory elements comprising: a first semiconductor protrusion extending from the lower surface of said substrate, said first protrusion having a side surface; a first impurity region formed in an upper portion of said first protrusion; a second impurity region formed within said lower surface of the semiconductor substrate adjacent to said first protrusion; a floating gate electrode adjacent to said side surface of the first protrusion, said floating gate electrode being insulated from said first protrusion by a first insulating layer therebetween; and a gate electrode formed adjacent to said floating gate electrode with a second insulating layer therebetween; and (3) a peripheral circuit comprising a plurality of MOS transistors, each of the MOS transistors comprising: a second semiconductor protrusion extending from the lower surface of said substrate, said second protrusion having a side surface; a first impurity region formed in an upper portion of said second protrusion; a second impurity region formed within said lower surface of the semiconductor substrate adjacent to said second protrusion; and a gate electrode adjacent to said side surface of the second protrusion, said gate electrode being insulated from said second protrusion by a gate insulating film therebetween.

Claim 29

A semiconductor device comprising: (1) a semiconductor substrate having a lower surface; (2) a memory circuit comprising a plurality of semiconductor memory elements, each of the semiconductor memory elements comprising: a first semiconductor protrusion extending from the lower surface of said substrate, said first protrusion having a side surface; a first impurity region formed in an upper portion of said first protrusion; a second impurity region formed within said lower surface of the semiconductor substrate adjacent to said first protrusion; a floating gate electrode adjacent to said side surface of the first protrusion, said floating gate electrode being insulated from said first protrusion by a first insulating layer therebetween; and a gate electrode formed adjacent to said floating gate electrode with a second insulating layer therebetween; and (3) a peripheral circuit comprising a plurality of MOS transistors, each of the MOS transistors comprising: a second semiconductor protrusion extending from the lower surface of said substrate, said second protrusion having a side surface; a first impurity region formed in an upper portion of said second protrusion; a second impurity region formed within said lower surface of the semiconductor substrate adjacent to said second protrusion; and a gate electrode adjacent to said side surface of the second protrusion, said gate electrode being insulated from said second protrusion by a gate insulating film therebetween.

Claim 30

A semiconductor device comprising: (1) a semiconductor substrate having a lower surface; (2) a memory circuit comprising a plurality of semiconductor memory elements, each of the semiconductor memory elements comprising: a first semiconductor protrusion extending from the lower surface of said substrate, said first protrusion having a side surface; a first impurity region formed in an upper portion of said first protrusion; a second impurity region formed within said lower surface of the semiconductor substrate adjacent to said first protrusion; a floating gate electrode adjacent to said side surface of the first protrusion, said floating gate electrode being insulated from said first protrusion by a first insulating layer therebetween; and a gate electrode formed adjacent to said floating gate electrode with a second insulating layer therebetween; and (3) a peripheral circuit comprising a plurality of MOS transistors, each of the MOS transistors comprising: a second semiconductor protrusion extending from the lower surface of said substrate, said second protrusion having a side surface; a first impurity region formed in an upper portion of said second protrusion; a second impurity region formed within said lower surface of the semiconductor substrate adjacent to said second protrusion; a pair of lightly doped regions in contact with said first and second impurity regions; and a gate electrode adjacent to said side surface of the second protrusion, said gate electrode being insulated from said second protrusion by a gate insulating film therebetween.

Claim 31

A semiconductor device comprising: (1) a semiconductor substrate having a lower surface; (2) a memory circuit comprising a plurality of semiconductor memory elements, each of the semiconductor memory elements comprising: a first semiconductor protrusion extending from the lower surface of said substrate, said first protrusion having a side surface; a first impurity region formed in an upper portion of said first protrusion; a second impurity region formed within said lower surface of the semiconductor substrate adjacent to said first protrusion; a floating gate electrode adjacent to said side surface of the first protrusion, said floating gate electrode being insulated from said first protrusion by a first insulating layer therebetween; and a gate electrode formed adjacent to said floating gate electrode with a second insulating layer therebetween; and (3) a peripheral circuit comprising a plurality of MOS transistors, each of the MOS transistors comprising: a second semiconductor protrusion extending from the lower surface of said substrate, said second protrusion having a side surface; a first impurity region formed in an upper portion of said second protrusion; a second impurity region formed within said lower surface of the semiconductor substrate adjacent to said second protrusion; a pair of lightly doped regions in contact with said first and second impurity regions; and a gate electrode adjacent to said side surface of the second protrusion, said gate electrode being insulated from said second protrusion by a gate insulating film therebetween.