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US5633209A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of forming a circuit membrane with a polysilicon film

Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1995-06-07
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Granted: 1997-05-27
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Expires: 2015-06-07
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Abstract

Abstract General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Inventors

  • 👤 Glenn J. Leedy

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-07 10:18
CPC Classifications
H; H10; H10P; H10P95/00; H10W; H10W90/00; G; G03; G03F; G03F7/00; G03F7/70; G03F7/70483; G03F7/70605; G03F7/70653; G03F7/70658; G11; G11C; G11C29/00; G11C29/006; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10W10/00; H10W10/01; H10W10/011; H10W10/021; H10W10/061; H10W10/10; H10W10/181; H10W10/20; H10W70/00; H10W70/60; H10W70/611; H10W70/62; H10W70/65; H10W70/67; H10W70/68; H10W70/685; H10W70/688; G02; G02F; G02F1/00; G02F1/01; G02F1/13; G02F1/133; G02F1/1333; G02F1/1345; G02F1/13452; G02F1/136; G02F1/1362; G02F1/136277; G02F1/136281; H10D; H10D84/00; H10D84/01; H10D84/02; H10D84/03; H10D84/038; H10D88/00; H10D88/01; H10D89/00; H10D89/10; H10W70/682; H10W72/00; H10W72/20; H10W72/221; H10W72/29; H10W72/90; H10W72/941; H10W72/942; H10W90/701; H10W90/721; H10W90/724; Y; Y10; Y10S; Y10S148/00; Y10S148/135; Y10S438/00; Y10S438/928; Y10S438/938; Y10S438/942; Y10S438/967; Y10S438/977; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/49128; Y10T29/49155; Y10T29/49162; Y10T29/49165; Y10T29/49169; Y10T29/49171; Y10T29/49204; Y10T29/49208; Y10T29/4921

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 72 words
A method of forming a circuit membrane comprising the steps of: providing a substrate having a principal surface and an opposing back surface; forming a tensile film of polysilicon on both the principal and back surfaces; depositing a low stress insulating membrane over the tensile film on the principal surface; and etching away a central portion of the film on the back surface, and etching away the underlying portion of the substrate.
Claim 2
Independent Claim 72 words
A method of forming a circuit membrane comprising the steps of: providing a substrate having a principal surface and an opposing back surface; forming a tensile film of polysilicon on both the principal and back surfaces; depositing a low stress insulating membrane over the tensile film on the principal surface; and etching away a central portion of the film on the back surface, and etching away the underlying portion of the substrate.

References Cited (Backward Citations)

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2000-05-26 2000-11-25 2001-05-27 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2004-05-26 2004-11-25 2005-05-27 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2008-05-26 2008-11-25 2009-05-27 $7700.00 Window Closed / Lapsed

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