US5633199A
Expired / Lapsed
US
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Process for fabricating a metallized interconnect structure in a semiconductor device
Assignee: Motorola Solutions Inc
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Filing: 1995-11-02
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Granted: 1997-05-27
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Expires: 2015-11-02
Abstract
Abstract A process for fabricating a metallized interconnect structure in a semiconductor device includes the steps of depositing a first aluminum layer (22) into a via opening (16) in a dielectric layer (18). A doping layer (24) is deposited by high density plasma sputtering to form a portion thereof in the bottom of the via opening (16). A second aluminum layer (26) is chemical vapor deposited to overlie the doping layer (24) and to fill the via opening (16). An annealing process can then be carried out to diffuse metal dopants from the doping layer (24) into nearby metal regions to provide a uniformly doped metal region within the via opening (16).
Inventors
- 👤 Robert W. Fiordalice
- 👤 Roc Blumenthal
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 02:19
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/056
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
107 words
A process for fabricating a metallized interconnect structure in a semiconductor device comprising the steps of: providing a dielectric layer having a via opening therein, wherein the via opening is characterized by substantially vertical sidewalls and a bottom surface; chemical vapor depositing a first aluminum layer to overlie the substantially vertical sidewalls and the bottom surface; forming a doping layer comprising chrome overlying the first aluminum layer, wherein the doping layer within the via opening is confined to a portion of the first aluminum layer overlying the bottom surface; and chemical vapor depositing a second aluminum layer to overlie the doping layer and to fill the via.
Claim 2
Dependent Claim
107 words
A process for fabricating a metallized interconnect structure in a semiconductor device comprising the steps of: providing a dielectric layer having a via opening therein, wherein the via opening is characterized by substantially vertical sidewalls and a bottom surface; chemical vapor depositing a first aluminum layer to overlie the substantially vertical sidewalls and the bottom surface; forming a doping layer comprising chrome overlying the first aluminum layer, wherein the doping layer within the via opening is confined to a portion of the first aluminum layer overlying the bottom surface; and chemical vapor depositing a second aluminum layer to overlie the doping layer and to fill the via.
Claim 3
Dependent Claim
20 words
The process of claim 1, wherein the step of forming a doping layer comprises plasma sputtering of an aluminum-chrome alloy.
Claim 4
Dependent Claim
129 words
A process for fabricating a metallized interconnect structure in a semiconductor device comprising the steps of: providing a substrate having a dielectric layer thereon, wherein the dielectric layer has an upper surface; forming an opening in the dielectric layer, wherein the opening is characterized by substantially vertical sidewalls and a bottom surface; chemical vapor depositing a first aluminum layer into the opening, wherein the first aluminum layer overlies the substantially vertical sidewalls and the bottom surface; sputtering a doping layer comprising copper onto the first aluminum layer, wherein the doping layer overlies the first aluminum layer at the bottom surface of the opening and at the upper surface of the dielectric layer; and chemical vapor depositing a second aluminum layer onto the second aluminum layer to fill the opening.
Claim 5
Dependent Claim
129 words
A process for fabricating a metallized interconnect structure in a semiconductor device comprising the steps of: providing a substrate having a dielectric layer thereon, wherein the dielectric layer has an upper surface; forming an opening in the dielectric layer, wherein the opening is characterized by substantially vertical sidewalls and a bottom surface; chemical vapor depositing a first aluminum layer into the opening, wherein the first aluminum layer overlies the substantially vertical sidewalls and the bottom surface; sputtering a doping layer comprising copper onto the first aluminum layer, wherein the doping layer overlies the first aluminum layer at the bottom surface of the opening and at the upper surface of the dielectric layer; and chemical vapor depositing a second aluminum layer onto the second aluminum layer to fill the opening.
Claim 6
Dependent Claim
28 words
The process of claim 3, wherein the step of sputtering a doping layer comprises sputtering a copper alloy selected from the group consisting of aluminum-copper and titanium copper.
Claim 7
Dependent Claim
20 words
The process of claim 3, wherein the step of sputtering a doping layer comprises sputtering a layer of copper metal.
Claim 8
Dependent Claim
22 words
The process of claim 3, wherein the step of sputtering a doping layer is further characterized as directionally sputtering the doping layer.
Claim 9
Dependent Claim
123 words
A process for fabricating a metallized interconnect structure in a semiconductor device comprising the steps of: providing a semiconductor substrate having a dielectric layer thereon, wherein the dielectric layer has an opening therein exposing a contact region of the semiconductor substrate; chemical vapor depositing a first metal layer comprising aluminum overlying the dielectric layer and the contact region of the semiconductor substrate; directionally depositing a doping layer into the opening, wherein the doping layer contains a metal impurity selected from the group consisting of copper, nickel and chrome; chemical vapor depositing a second metal layer comprising aluminum to overlie the doping layer and fill the opening; and annealing the semiconductor substrate to diffuse the metal impurity into the first and second metal layers.
Claim 10
Dependent Claim
123 words
A process for fabricating a metallized interconnect structure in a semiconductor device comprising the steps of: providing a semiconductor substrate having a dielectric layer thereon, wherein the dielectric layer has an opening therein exposing a contact region of the semiconductor substrate; chemical vapor depositing a first metal layer comprising aluminum overlying the dielectric layer and the contact region of the semiconductor substrate; directionally depositing a doping layer into the opening, wherein the doping layer contains a metal impurity selected from the group consisting of copper, nickel and chrome; chemical vapor depositing a second metal layer comprising aluminum to overlie the doping layer and fill the opening; and annealing the semiconductor substrate to diffuse the metal impurity into the first and second metal layers.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-05-26 | 2000-11-25 | 2001-05-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-05-26 | 2004-11-25 | 2005-05-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-05-26 | 2008-11-25 | 2009-05-27 | $7700.00 | Window Closed / Lapsed |