US5632037A
Expired / Lapsed
US
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Microprocessor having power management circuitry with coprocessor support
Assignee: National Semiconductor Corp
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Filing: 1992-03-27
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Granted: 1997-05-20
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Expires: 2012-03-27
Abstract
Abstract A processing unit includes a plurality of subcircuits and circuitry for generating clock signals thereto. Detecting circuitry detects the assertion of a first signal indicative of a request for suspending operation of the processing unit and the assertion of a second signal indicating the state of operation of a coprocessing unit. Disabling circuitry is operable to disable clock signals to one or more of the subcircuits responsive to the first and second control signals.
Inventors
- 👤 Robert Maher
- 👤 Raul A. Garibay, Jr.
- 👤 Margaret R. Herubin
- 👤 Mark Bluhm
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 01:39
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30076; G06F9/30083; G06F1/00; G06F1/26; G06F1/32; G06F1/3203; G06F1/3234; G06F1/3237; G06F9/30079; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
119 words
A microprocessor having power management circuitry with coprocessor support, comprising: (a) clock generation means for supplying a first and a second clock signal; (b) core means, coupled to the clock generation means to receive the first clock signal, for executing instructions; (c) memory management means, coupled to the clock generation means to receive the first clock signal, for managing memory access; and, (d) bus controller means, coupled to the clock generation means to receive the second clock signal, and to an external source to receive a suspend request signal, and to a coprocessor to receive a busy signal, for disabling the first clock signal in response to the suspend request signal being asserted and the busy signal being de-asserted.
Claim 2
Dependent Claim
119 words
A microprocessor having power management circuitry with coprocessor support, comprising: (a) clock generation means for supplying a first and a second clock signal; (b) core means, coupled to the clock generation means to receive the first clock signal, for executing instructions; (c) memory management means, coupled to the clock generation means to receive the first clock signal, for managing memory access; and, (d) bus controller means, coupled to the clock generation means to receive the second clock signal, and to an external source to receive a suspend request signal, and to a coprocessor to receive a busy signal, for disabling the first clock signal in response to the suspend request signal being asserted and the busy signal being de-asserted.
Claim 3
Dependent Claim
25 words
A microprocessor as recited in claim 1 wherein the bus controller means further includes an output to acknowledge that the first clock signal is disabled.
Claim 4
Dependent Claim
144 words
A computer system employing a microprocessor having power management circuitry with coprocessor support, comprising: (a) a memory; (b) a BIOS ROM; (c) chipset logic providing a suspend request signal; (d) a coprocessor providing a busy signal; and (e) a microprocessor including clock circuitry, core circuitry, memory management circuitry, and bus control circuitry, coupled to the memory, the BIOS ROM, the chipset logic, and the coprocessor to receive signals therefrom, the clock circuitry being coupled to the core circuitry, the memory management circuitry, and the bus control circuitry, the bus control circuitry having inputs coupled to the suspend request signal and the busy signal, in response to the suspend request signal being asserted and the busy signal being de-asserted, the bus control circuitry disabling the clock circuitry to the core circuitry and the memory management circuitry so that power consumption in the microprocessor is reduced.
Claim 5
Dependent Claim
144 words
A computer system employing a microprocessor having power management circuitry with coprocessor support, comprising: (a) a memory; (b) a BIOS ROM; (c) chipset logic providing a suspend request signal; (d) a coprocessor providing a busy signal; and (e) a microprocessor including clock circuitry, core circuitry, memory management circuitry, and bus control circuitry, coupled to the memory, the BIOS ROM, the chipset logic, and the coprocessor to receive signals therefrom, the clock circuitry being coupled to the core circuitry, the memory management circuitry, and the bus control circuitry, the bus control circuitry having inputs coupled to the suspend request signal and the busy signal, in response to the suspend request signal being asserted and the busy signal being de-asserted, the bus control circuitry disabling the clock circuitry to the core circuitry and the memory management circuitry so that power consumption in the microprocessor is reduced.
Claim 6
Dependent Claim
41 words
A computer system as recited in claim 3 wherein the microprocessor further provides a suspend acknowledge signal to the chipset logic in response to the bus control circuitry disabling the clock circuitry to the core circuitry and the memory management circuitry.
Claim 7
Dependent Claim
55 words
A computer system as recited in claim 4 further comprising a system clock generator providing a system clock signal to the chipset logic, to the coprocessor, and to the clock circuitry in the microprocessor, in response to receiving the suspend acknowledge signal, the chipset logic disables the system clock from the microprocessor and the coprocessor.
Claim 8
Dependent Claim
82 words
In a computer system having a coprocessor and a microprocessor including clock circuitry, core circuitry, memory management circuitry, and bus control circuitry, a method of power management comprising the steps of: (a) receiving a request from an external source to suspend the clock circuitry into the bus control circuitry; (b) checking that a busy signal received from the coprocessor is de-asserted; and, (c) suspending the clock circuitry to the core circuitry and memory management circuitry in response to steps (a) and (b).
Claim 9
Dependent Claim
82 words
In a computer system having a coprocessor and a microprocessor including clock circuitry, core circuitry, memory management circuitry, and bus control circuitry, a method of power management comprising the steps of: (a) receiving a request from an external source to suspend the clock circuitry into the bus control circuitry; (b) checking that a busy signal received from the coprocessor is de-asserted; and, (c) suspending the clock circuitry to the core circuitry and memory management circuitry in response to steps (a) and (b).
Claim 10
Dependent Claim
23 words
A method as recited in claim 6 further comprising step (d) acknowledging that the core circuitry and the memory management circuitry are suspended.
Claim 11
Dependent Claim
24 words
A method as recited in claim 7 further comprising step (e) disabling a system clock to the clock circuitry in response to step (d).
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-05-19 | 2000-11-18 | 2001-05-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-05-19 | 2004-11-18 | 2005-05-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-05-19 | 2008-11-18 | 2009-05-20 | $7700.00 | Window Closed / Lapsed |