Register circuit

Claim 2

A register circuit comprising: a quantizing circuit having an input terminal for receiving an analog input voltage and an output terminal for outputting a quantized voltage of said analog input voltage according to predetermined quantizing levels; and a switching circuit for alternatively connecting at least one of said analog input voltage and an output of said quantizing circuit to said input terminal.

Claim 3

A register circuit as claimed in claim 1, wherein said quantizing circuit comprises: a plurality of thresholding circuits with a common threshold voltage, each of said thresholding circuits having an input terminal and an output terminal, wherein each of said thresholding circuits has a different quantizing level; and a plurality of capacitive couplings each of which is provided for one of said thresholding circuits for weighting and adding said analog input voltage to an output at each said output terminal from each of said thresholding circuits having a higher quantizing level.

Claim 4

A register circuit as claimed in claim 2, wherein said thresholding circuit inverts an input at said input terminal when said input exceeds said threshold voltage of said thresholding circuit.

Claim 5

A register circuit as claimed in claim 3, wherein: said weights of said capacitive couplings of said thresholding circuits are 2 1 , 2 2 , . . . , 2 k for outputs from thresholding circuits with higher quantization levels ranging from 1 to k levels, respectively, and a weight of 2 m+1 for said analog input voltage into each said thresholding circuit, where m is the number of said thresholding circuits.

Claim 6

A register circuit as claimed in claim 4, further comprising a capacitive coupling for adding said outputs of said thresholding circuits with weights of 2 1 , 2 2 , . . . 2 m for the lowest threshold, the second threshold, . . . the highest threshold, respectively, whereby a complement of said quantized input voltage is outputted.

Claim 7

A register circuit as claimed in claim 4 further comprising a plurality of inverters for inverting a plurality of outputs from said thresholding circuits and a capacitive coupling for adding said outputs of said inverters with weights of 2 1 , 2 2 , . . . , 2 m for the lowest threshold circuit the second threshold circuit, . . . , the highest threshold circuit, respectively, whereby a quantized voltage is output.

Claim 8

A register circuit as claimed in claim 2, wherein a total of outputs from said thresholding circuits are output from said output terminals in parallel as multi-bit data.

Claim 9

A register circuit comprising a first flip-flop and a second flip-flop, said first flip-flop including: a first quantizing circuit having a first input terminal for receiving a first analog input voltage and an output terminal for outputting a first quantization of said first analog input voltage according to first predetermined quantizing levels, and a switching circuit for alternatively connecting one of said first analog input voltage and an output of said first quantizing circuit to said first input terminal; and said second flip-flop including: a second quantizing circuit having a second input terminal for receiving a second analog input voltage and an output terminal for outputting a second quantization of said second analog input voltage according to second predetermined quantization levels, and a switching circuit for alternatively connecting one of an output of said first flip-flop and an output of said second quantizing circuit to said second input terminal; and wherein, said switching circuits of said first and said second flip-flops are controlled by a clock, timings of said clock for said first flip-flop being reversed from timings of said clock for said second flip-flop.

Claim 10

A register circuit comprising a first flip-flop and a second flip-flop, said first flip-flop including: a first quantizing circuit having a first input terminal for receiving a first analog input voltage and an output terminal for outputting a first quantization of said first analog input voltage according to first predetermined quantizing levels, and a switching circuit for alternatively connecting one of said first analog input voltage and an output of said first quantizing circuit to said first input terminal; and said second flip-flop including: a second quantizing circuit having a second input terminal for receiving a second analog input voltage and an output terminal for outputting a second quantization of said second analog input voltage according to second predetermined quantization levels, and a switching circuit for alternatively connecting one of an output of said first flip-flop and an output of said second quantizing circuit to said second input terminal; and wherein, said switching circuits of said first and said second flip-flops are controlled by a clock, timings of said clock for said first flip-flop being reversed from timings of said clock for said second flip-flop.

Claim 11

A register circuit comprising: a first flip-flop comprising: a first quantizing circuit having a first input terminal for receiving a first analog input voltage and an output terminal for outputting a first quantization of said first analog input voltage according to first predetermined quantization levels, and a first switching circuit for selectively connecting one of said first analog input voltage, said first output of said quantizing circuit, a third input and a fourth input to said first input terminal; a second flip-flop comprising: a second quantizing circuit having a second input terminal for receiving an analog input voltage and a second output terminal for outputting a second quantization of said second analog input voltage according to second predetermined quantization levels, and a second switching circuit for selectively connecting one of an output of said first flip-flop and an output of said second quantizing circuit to said second input terminal; an increment circuit connected to said output of said second quantizing circuit for outputting a minimum value when said second quantization is a maximum value and otherwise for outputting a value one less than said second quantization as said third input of said first switching circuit; and a decrement circuit connected to said output of said second quantizing circuit for outputting a maximum value when said second quantization is a minimum value and otherwise for outputting a value one more than said second quantization as said fourth input of said first switching circuit.

Claim 12

A register circuit comprising: a first flip-flop comprising: a first quantizing circuit having a first input terminal for receiving a first analog input voltage and an output terminal for outputting a first quantization of said first analog input voltage according to first predetermined quantization levels, and a first switching circuit for selectively connecting one of said first analog input voltage, said first output of said quantizing circuit, a third input and a fourth input to said first input terminal; a second flip-flop comprising: a second quantizing circuit having a second input terminal for receiving an analog input voltage and a second output terminal for outputting a second quantization of said second analog input voltage according to second predetermined quantization levels, and a second switching circuit for selectively connecting one of an output of said first flip-flop and an output of said second quantizing circuit to said second input terminal; an increment circuit connected to said output of said second quantizing circuit for outputting a minimum value when said second quantization is a maximum value and otherwise for outputting a value one less than said second quantization as said third input of said first switching circuit; and a decrement circuit connected to said output of said second quantizing circuit for outputting a maximum value when said second quantization is a minimum value and otherwise for outputting a value one more than said second quantization as said fourth input of said first switching circuit.

Claim 13

A register circuit as claimed in claim 9, further comprising a circuit for outputting a carry signal when one of said quantizing circuits outputs a minimum value and a different one of said quantizing circuits outputs a maximum value.

Claim 14

A register circuit comprising: a quantizing circuit having an input terminal for receiving an analog input voltage and an output terminal for outputting a quantization of said analog input voltage according to predetermined quantizing levels, wherein said quantizing circuit comprises: a plurality of thresholding circuits, each thresholding circuit having a common threshold voltage and each having an input terminal and an output terminal, and a plurality of capacitive couplings corresponding to said plurality of thresholding circuits, respectively, at least one of said capacitive couplings weighing and adding said analog input voltage to an output of each thresholding circuit having a higher quantizing level; a holding circuit for holding said quantized voltage; and a switching circuit for alternatively connecting at least one of said analog input voltage and an output of said holding circuit to said input terminal of said quantizing circuit.

Claim 15

A register circuit comprising: a quantizing circuit having an input terminal for receiving an analog input voltage and an output terminal for outputting a quantization of said analog input voltage according to predetermined quantizing levels, wherein said quantizing circuit comprises: a plurality of thresholding circuits, each thresholding circuit having a common threshold voltage and each having an input terminal and an output terminal, and a plurality of capacitive couplings corresponding to said plurality of thresholding circuits, respectively, at least one of said capacitive couplings weighing and adding said analog input voltage to an output of each thresholding circuit having a higher quantizing level; a holding circuit for holding said quantized voltage; and a switching circuit for alternatively connecting at least one of said analog input voltage and an output of said holding circuit to said input terminal of said quantizing circuit.

Claim 16

A register circuit comprising: a plurality of bi-stable circuits which invert outputs at different stepwise thresholds: and a capacitive coupling for receiving a total of outputs from said bi-stable circuits and for outputting a weighted addition of said outputs.

Claim 17

A register circuit comprising: a plurality of bi-stable circuits which invert outputs at different stepwise thresholds: and a capacitive coupling for receiving a total of outputs from said bi-stable circuits and for outputting a weighted addition of said outputs.