US5631912A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High impedance test mode for JTAG
Assignee: Samsung Electronics Co Ltd
•
Filing: 1995-12-19
•
Granted: 1997-05-20
•
Expires: 2015-12-19
Abstract
Abstract A specially configured JTAG test circuit allows multiple bus connections within an integrated circuit chip to be selectively placed in a high impedance state in an efficient manner. The output enable shift register locations are placed in close logical proximity to one another along the JTAG data shift register boundary scan path so that data bits need not be shifted into all of the data shift register locations within the integrated circuit chip in order to selectively enable and disable the several bus interfaces within the integrated circuit chip. In this manner, the integrated circuit chip may be isolated from selected ones of the buses connected to the integrated circuit chip, while other bus connections can remain enabled to drive others of the buses connected to the integrated circuit chip. Thus, problems associated with setting the entire integrated circuit chip in a high impedance mode are avoided.
Inventors
- 👤 L. Randall Mote, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 08:25
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318558
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
316 words
A JTAG test circuit architecture for selectively enabling and disabling peripheral connections to an integrated circuit (IC), said architecture comprising: a boundary scan latch register including a plurality of data bit locations in electrical communication with said peripheral connections and in electrical communication with a plurality of output enable bit locations, each of said output enable bit locations used to enable the output of data bits stored in multiple ones of said data bit locations, wherein information stored in said output enable bit locations selectively places a plurality of said peripheral connections in a high impedance mode to selectively disable electrical communication between said data bit locations and said peripheral connections; and a boundary scan shift register which connects to said latch register so that contents of said shift register are parallel loaded into said latch register, said shift register including shift register data bit locations corresponding to said plurality of data bit locations in said latch register and including shift register output enable bit locations corresponding to said output enable bit locations in said latch register, said shift register output enable bit locations being grouped in close logical proximity within said shift register so that said shift register output enable bit locations are logically spaced apart by fewer shift register locations than the number of data bit locations enabled by each of said output enable bit locations; and a switching circuit which provides a first path through only said shift register output enable bit locations in close logical proximity while said switching circuit is in a first state, and which provides a second path through said shift register output enable bit locations and through said shift register data bit locations while said switching circuit is in a second state, said first path permitting states of said shift register output enable bit locations to be changed without changing states of said shift register data bit locations.
Claim 2
Dependent Claim
316 words
A JTAG test circuit architecture for selectively enabling and disabling peripheral connections to an integrated circuit (IC), said architecture comprising: a boundary scan latch register including a plurality of data bit locations in electrical communication with said peripheral connections and in electrical communication with a plurality of output enable bit locations, each of said output enable bit locations used to enable the output of data bits stored in multiple ones of said data bit locations, wherein information stored in said output enable bit locations selectively places a plurality of said peripheral connections in a high impedance mode to selectively disable electrical communication between said data bit locations and said peripheral connections; and a boundary scan shift register which connects to said latch register so that contents of said shift register are parallel loaded into said latch register, said shift register including shift register data bit locations corresponding to said plurality of data bit locations in said latch register and including shift register output enable bit locations corresponding to said output enable bit locations in said latch register, said shift register output enable bit locations being grouped in close logical proximity within said shift register so that said shift register output enable bit locations are logically spaced apart by fewer shift register locations than the number of data bit locations enabled by each of said output enable bit locations; and a switching circuit which provides a first path through only said shift register output enable bit locations in close logical proximity while said switching circuit is in a first state, and which provides a second path through said shift register output enable bit locations and through said shift register data bit locations while said switching circuit is in a second state, said first path permitting states of said shift register output enable bit locations to be changed without changing states of said shift register data bit locations.
Claim 3
Dependent Claim
29 words
A JTAG test circuit architecture as defined in claim 1, wherein said shift register output enable bit locations are connected in series and are logically adjacent to one another.
Claim 4
Dependent Claim
17 words
A JTAG test circuit architecture as defined in claim 1, wherein said switching circuit comprises a multiplexer.
Claim 5
Dependent Claim
19 words
A JTAG test circuit architecture as defined in claim 1, wherein said switching circuit connects to a JTAG output.
Claim 6
Independent Claim
197 words
A method of selectively enabling and disabling peripheral connections to an integrated circuit (IC) using a JTAG boundary scan test circuit having a plurality of shift register output enable elements being grouped in close logical proximity within a serial boundary scan shift register so that said shift register output enable bit locations are logically spaced apart by fewer shift register elements than the number of data test bit locations enabled by each of a plurality of output enable elements, said method comprising the steps of: connecting said output enable elements and data test bit elements within said serial boundary scan shift register so that a first path is provided through said output enable elements and data test bit elements and a second path is provided only through said output enable elements, wherein information stored in said output enable elements selectively places a plurality of said peripheral connections in a high impedance mode to selectively disable electrical communication between said data test bit elements and said peripheral connections; generating a bit stream used for JTAG boundary scan testing; selecting between said first and second paths; and shifting said generated bit stream through said serial boundary scan shift register.
Claim 7
Independent Claim
197 words
A method of selectively enabling and disabling peripheral connections to an integrated circuit (IC) using a JTAG boundary scan test circuit having a plurality of shift register output enable elements being grouped in close logical proximity within a serial boundary scan shift register so that said shift register output enable bit locations are logically spaced apart by fewer shift register elements than the number of data test bit locations enabled by each of a plurality of output enable elements, said method comprising the steps of: connecting said output enable elements and data test bit elements within said serial boundary scan shift register so that a first path is provided through said output enable elements and data test bit elements and a second path is provided only through said output enable elements, wherein information stored in said output enable elements selectively places a plurality of said peripheral connections in a high impedance mode to selectively disable electrical communication between said data test bit elements and said peripheral connections; generating a bit stream used for JTAG boundary scan testing; selecting between said first and second paths; and shifting said generated bit stream through said serial boundary scan shift register.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-05-19 | 2000-11-18 | 2001-05-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-05-19 | 2004-11-18 | 2005-05-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-05-19 | 2008-11-18 | 2009-05-20 | $7700.00 | Window Closed / Lapsed |