US5631599A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Two stage current mirror
Assignee: Intersil Corp
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Filing: 1995-12-13
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Granted: 1997-05-20
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Expires: 2015-12-13
Abstract
Abstract An A-to-D converter 300 has a comparator 126 with a number of comparator cells 902. Each comparator cell 902 includes a current mirror 1700 that reduces kickback noise. Current mirror 1700 includes a bipolar current mirror 1705 and an NMOS current mirror 1709. The bipolar current mirror 1705 provides an ac ground paralleling NMOS transistor 1704 in the NMOS current mirror 1709 to reduce kickback noise.
Inventors
- 👤 Kantilal Bacrania
- 👤 Chong I. Chi
- 👤 Gregory J. Fisher
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 22:36
CPC Classifications
H; H03; H03G; H03G1/00; H03G1/0005; H03G1/0035; H03G1/0082; G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/26; G05F3/262; G05F3/30; G11; G11C; G11C27/00; G11C27/02; G11C27/024; G11C27/026; H03F; H03F1/00; H03F1/52; H03F1/523; H03F3/00; H03F3/50; H03F3/505; H03K; H03K17/00; H03K17/22; H03K17/223; H03K5/00; H03K5/15; H03M; H03M1/00; H03M1/12; H03M1/14; H03M1/16; H03M1/162; H10; H10D; H10D84/00; H10D84/40; H10D84/401; H10D88/00; H10D89/00; H10D89/211; H03F2200/00; H03F2200/294; H03M1/34; H03M1/36; H03M1/361; H03M1/362; H03M1/365
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
176 words
A current mirror, comprising: (a) a first stage comprising a reference current input for receiving a reference current, a first bipolar transistor coupled to the reference current input and having an emitter current representative of the reference current; voltage generating means for generating a voltage proportional to a current, said voltage generating means coupled to the emitter of the first bipolar transistor for generating a voltage proportional to the emitter current of the first bipolar transistor; a second bipolar transistor coupled to the first bipolar transistor and to the output of the first stage for generating at the emitter of the second bipolar transistor a controlled voltage representative of the reference current; (b) a second stage with a second stage input coupled to the output of the first stage, said second stage comprising one or more output field effect transistors (FETs) with their gates coupled to the controlled voltage for generating second stage output currents in the output FETs proportional to the controlled voltage of the first stage output and representative of the reference input current.
Claim 2
Dependent Claim
176 words
A current mirror, comprising: (a) a first stage comprising a reference current input for receiving a reference current, a first bipolar transistor coupled to the reference current input and having an emitter current representative of the reference current; voltage generating means for generating a voltage proportional to a current, said voltage generating means coupled to the emitter of the first bipolar transistor for generating a voltage proportional to the emitter current of the first bipolar transistor; a second bipolar transistor coupled to the first bipolar transistor and to the output of the first stage for generating at the emitter of the second bipolar transistor a controlled voltage representative of the reference current; (b) a second stage with a second stage input coupled to the output of the first stage, said second stage comprising one or more output field effect transistors (FETs) with their gates coupled to the controlled voltage for generating second stage output currents in the output FETs proportional to the controlled voltage of the first stage output and representative of the reference input current.
Claim 3
Dependent Claim
20 words
The current mirror of claim 1 wherein the controlled voltage corresponds to the voltage generated by the voltage generating means.
Claim 4
Dependent Claim
21 words
The current mirror of claim 1 wherein the bases of the first and second bipolar transistors are connected to each other.
Claim 5
Dependent Claim
21 words
The current mirror of claim 1 wherein the two bipolar transistors are NPN transistors and the output FETs are NMOS transistors.
Claim 6
Dependent Claim
17 words
The current mirror of claim 4 wherein the voltage generating means comprises a diode connected NMOS transistor.
Claim 7
Dependent Claim
21 words
The current mirror of claim 1 wherein the two bipolar transistors are PNP transistors and the output FETs are PMOS transistors.
Claim 8
Dependent Claim
17 words
The current mirror of claim 6 wherein the voltage generating means comprises a diode connected PMOS transistor.
Claim 9
Dependent Claim
33 words
The current mirror of claim 1 wherein the second stage further comprises current generating means coupled to the emitter of the second bipolar transistor for generating a current proportional to the emitter voltage.
Claim 10
Dependent Claim
27 words
The current mirror of claim 8 wherein the voltage generating means of the first stage and the current generating means of the second stage are identical FETs.
Claim 11
Dependent Claim
17 words
The current mirror of claim 8 wherein the current generating means comprises a diode connected NMOS transistor.
Claim 12
Dependent Claim
24 words
The current mirror of claim 10 wherein the gate and the drain of the current generating NMOS transistor are connected to the controlled voltage.
Claim 13
Dependent Claim
17 words
The current mirror of claim 8 wherein the current generating means comprises a diode connected PMOS transistor.
Claim 14
Dependent Claim
24 words
The current mirror of claim 12 wherein the gate and the drain of the current generating PMOS transistor are connected to the controlled voltage.
Claim 15
Dependent Claim
38 words
The current mirror of claim 1 wherein the first stage further comprises base compensation circuitry connected to the bases of the first and second bipolar transistors for compensating the base current of the first and second bipolar transistors.
Claim 16
Dependent Claim
39 words
The current mirror of claim 14 wherein the base compensation circuitry comprises a third bipolar transistor having its base coupled to the collector of the first transistor and its emitter coupled to the base of the second bipolar transistor.
Claim 17
Dependent Claim
35 words
The current mirror of claim 15 wherein the base compensation circuitry further comprises a fourth bipolar transistor in series with a FET for further compensating the base current in the first and second bipolar transistors.
Claim 18
Dependent Claim
56 words
The current mirror of claim 1 wherein the diode connected FET provides a first impedance path for spurious signals on the gates of the output FETS and the second bipolar transistor provides a second impedance path for such spurious gate signals, said second impedance path being substantially less than the impedance of the first impedance path.
Claim 19
Dependent Claim
28 words
The current mirror of claim 1 wherein each of the first bipolar transistor, the voltage generating means and each output FET is serially connected to a diode-connected FET.
Claim 20
Independent Claim
100 words
A method of mirroring currents, comprising the steps of: providing first and second stages in a current mirror, said first stage comprising first and second bipolar transistors; providing an input reference current to the collector of the first bipolar transistor; generating a voltage at the emitter of the first transistor representative of the input reference current; generating a controlled output voltage at the emitter of the second bipolar transistor representative of the input reference current; connecting gates of one or more output FETs to the controlled voltage to provide one or more output currents representative of the input reference current.
Claim 21
Independent Claim
100 words
A method of mirroring currents, comprising the steps of: providing first and second stages in a current mirror, said first stage comprising first and second bipolar transistors; providing an input reference current to the collector of the first bipolar transistor; generating a voltage at the emitter of the first transistor representative of the input reference current; generating a controlled output voltage at the emitter of the second bipolar transistor representative of the input reference current; connecting gates of one or more output FETs to the controlled voltage to provide one or more output currents representative of the input reference current.
Claim 22
Dependent Claim
30 words
The method of claim 19 wherein the voltage generated at the emitter of the first bipolar transistor corresponds to the controlled voltage at the emitter of the second bipolar transistor.
Claim 23
Dependent Claim
18 words
The method of claim 19 wherein the bipolar transistors are NPN transistors and the FETs are NMOS FETs.
Claim 24
Dependent Claim
18 words
The method of claim 19 wherein the bipolar transistors are PNP transistors and the FETs are PMOS FETs.
Claim 25
Dependent Claim
19 words
The method of claim 19 further comprising the step of generating a current proportional to the second emitter voltage.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-05-19 | 2000-11-18 | 2001-05-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-05-19 | 2004-11-18 | 2005-05-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-05-19 | 2008-11-18 | 2009-05-20 | $7700.00 | Window Closed / Lapsed |