US4618816A
Expired / Lapsed
US
⏱️ 0.0 years remaining
CMOS ΔVBE bias current generator
Assignee: National Semiconductor Corp
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Filing: 1985-08-22
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Granted: 1986-10-21
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Expires: 2005-08-22
Abstract
Abstract In a CMOS structure a pair of BJTs are provided with lateral collectors and operated at different current densities. The lateral collectors are coupled to a current mirror load which provides a single ended output node. The pair bases are coupled together and to the current mirror load input so that the lateral BJT collectors operate at low potential. A current source supplies tail current and a resistor is coupled in series with the low current density BJT. The single ended output node is coupled to a current mirror that determines the BJT tail current. The circuit therefore has a negative feedback loop around the BJTs that will stabilize operation so that ΔV BE appears across the resistor. The resistor can be chosen so that the overall circuit temperature coefficient can be established at a desired value.
Inventors
- 👤 Dennis M. Monticelli
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 14:07
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/30
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
156 words
A bias current generator circuit for implementation in CMOS construction, said circuit comprising: first and second BJTs, each one having a base, an emitter, a substrate dedicated collector and a lateral collector with the two collectors sharing the emitter current; means for operating said first BJT at a higher emitter current density than said second BJT; means for coupling the bases of said first and second BJTs together and to said lateral collector of said first BJT; first and second IGFETS coupled together as a current mirror load for said lateral collectors of said BJTs; means for coupling the emitter of said first BJT to a tail current source; a resistor coupled between the emitter of said second BJT and said tail current source; and means for modulating said tail current source in response to the potential at said second BJT lateral collector whereby said circuit is stabilized and the potential across said resistor is PTAT.
Claim 2
Dependent Claim
156 words
A bias current generator circuit for implementation in CMOS construction, said circuit comprising: first and second BJTs, each one having a base, an emitter, a substrate dedicated collector and a lateral collector with the two collectors sharing the emitter current; means for operating said first BJT at a higher emitter current density than said second BJT; means for coupling the bases of said first and second BJTs together and to said lateral collector of said first BJT; first and second IGFETS coupled together as a current mirror load for said lateral collectors of said BJTs; means for coupling the emitter of said first BJT to a tail current source; a resistor coupled between the emitter of said second BJT and said tail current source; and means for modulating said tail current source in response to the potential at said second BJT lateral collector whereby said circuit is stabilized and the potential across said resistor is PTAT.
Claim 3
Dependent Claim
37 words
The circuit of claim 1 wherein said first and second IGFETs are matched whereby said first and second BJTs conduct equally and said second BJT is made to have a larger emitter area than said first BJT.
Claim 4
Dependent Claim
52 words
The circuit of claim 1 wherein said means for modulating further comprises a third IGFET having its gate electrode coupled to said lateral collector of said second BJT and its drain terminal coupled to the input of a current mirror whose output draws the current related to the potential across said resistor.
Claim 5
Dependent Claim
31 words
The circuit of claim 3 wherein said third IGFET is coupled to at least one more additional IGFET which will carry a current ratioed to that carried by said third IGFET.
Claim 6
Dependent Claim
31 words
The circuit of claim 3 wherein said current mirror is coupled to at least one more additional IGFET that will carry a current ratioed to that carried by said current mirror.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-10-20 | 1990-04-21 | 1990-10-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-10-20 | 1994-04-21 | 1994-10-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-10-20 | 1998-04-21 | 1998-10-21 | $7700.00 | Window Closed / Lapsed |