US4323795A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Bias current network for IC digital-to-analog converters and the like
Assignee: Analog Devices Inc
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Filing: 1980-02-12
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Granted: 1982-04-06
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Expires: 2000-02-12
Abstract
Abstract A single-chip 8-bit DAC with bipolar current sources, an output buffer amplifier for developing an output voltage, a regulated reference for producing a calibrated output, and operated by a single-voltage supply, e.g. +5 volts. The buffer amplifier includes means providing for driving the output voltage virtually to ground level when the DAC output is zero. The current sources comprise a single-transistor cell driven by an I 2 L flip-flop circuit, and the reference supply is merged with the reference transistor circuit regulating the DAC current levels, both aiding in reducing required chip area. A highly efficient bias network is utilized to supply the high-level bias currents required.
Inventors
- 👤 Peter R. Holloway
- 👤 Douglas A. Mercer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 10:15
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/26; G05F3/265; H; H03; H03M; H03M1/00; H03M1/66; H03M1/74
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
125 words
In an IC signal translation device such as a digital-to-analog converter having a plurality of circuit sections requiring individual bias currents, a bias supply circuit comprising: a PNP transistor with a split collector, said transistor being operated in high level injection; means connecting one of said collectors and the base of said transistor to a current mirror; control means responsive to the base current and the current in said one collector for setting the current mirror ratio to a predetermined value; means for combining said base current with said one collector current to supply one of said circuit sections with bias current; and means connecting the other collectors of said transistor to said other circuit sections respectively, to supply them with their individual bias currents.
Claim 2
Dependent Claim
125 words
In an IC signal translation device such as a digital-to-analog converter having a plurality of circuit sections requiring individual bias currents, a bias supply circuit comprising: a PNP transistor with a split collector, said transistor being operated in high level injection; means connecting one of said collectors and the base of said transistor to a current mirror; control means responsive to the base current and the current in said one collector for setting the current mirror ratio to a predetermined value; means for combining said base current with said one collector current to supply one of said circuit sections with bias current; and means connecting the other collectors of said transistor to said other circuit sections respectively, to supply them with their individual bias currents.
Claim 3
Dependent Claim
34 words
A device as in claim 1 wherein said current mirror comprises an NPN feedback transistor having its base connected to said one collector and its collector connected to the base of said PNP transistor.
Claim 4
Dependent Claim
74 words
A device as in claim 2, wherein said control means comprises a pair of NPN transistors with their bases connected together; means connecting said one collector to the collector of one of said pair of transistors; means connecting the emitter of said one NPN transistor to the collector and base of the other of said pair of transistors; and means connecting the emitters of said pair of transistors together and to said combining means.
Claim 5
Dependent Claim
22 words
A device as in claim 3, including a field-effect transistor connected between the base of said PNP transistor and said combining means.
Claim 6
Dependent Claim
31 words
A device as in claim 1, wherein said device includes both bipolar transistors and inverted-mode transistors; and means connecting said combining means to the main injector rail of said inverted-mode transistors.
Claim 7
Dependent Claim
16 words
A device as in claim 5, wherein one of said circuit sections comprises an ECL circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-04-05 | 1985-10-05 | 1986-04-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-04-05 | 1989-10-05 | 1990-04-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-04-05 | 1993-10-05 | 1994-04-06 | $7700.00 | Window Closed / Lapsed |