Crosspoint bias circuit arrangement

Claim 2

A semiconductor transmission circuit arrangement comprising: a symmetrical transmission switching transistor comprising first and second emitter/collector transmission terminals and a base terminal; and a high impedance bias circuit arrangement connected to one of said emitter/collector transmission terminals and to said base terminal and comprising regulating means for selectively maintaining direct currents of equal amplitude in said base and in the circuit including said connected one pf said emitter/collector terminals.

Claim 3

A semiconductor transmission switching arrangement comprising: a symmetrical transmission switching transistor comprising first and second emitter/collector transmission terminals and a base terminal; and a high impedance bias circuit arrangement comprising independent means connected respectively to said first and said second emitter/collector transmission terminals and to said base terminal, and comprising regulating means for selectively maintaining the sum of direct currents in said emitter/collectors equal in amplitude to the current in said base.

Claim 4

A semiconductor transmission switching arrangement comprising: a symmetrical transmission switching transistor comprising first and second emitter/collector transmission terminals and a base terminal; and a high impedance bias circuit arrangement comprising independent means connected respectively to said first and said second emitter/collector transmission terminals and to said base terminal, and comprising regulating means for selectively maintaining the sum of direct currents in said emitter/collectors equal in amplitude to the current in said base.

Claim 5

A semiconductor transmission circuit arrangement comprising: a symmetrical, bipolar, bilateral transmission transistor comprising first and second emitter/collector terminals and a base terminal; a first controllable high impedance current source circuit connected to one of said emitter/collector terminals for selectively maintaining a first constant magnitude direct current signal in a circuit including said connected one of said emitter/collector terminals; a second controllable high impedance current source circuit for selectively supplying a second constant magnitude direct current signal; current regulating means comprising first and second terminals connected respectively to said base terminal and to said second current source circuit and comprising means for maintaining the base current of said transmission transistor equal in magnitude to said first constant current signal, said base current being of a magnitude sufficient to saturate said transmission transistor for a substantial range of a.c. signals supplied to said emitter/collector terminals; and means for generating signals for controlling said first and second current source circuits.

Claim 6

A semiconductor transmission circuit arrangement comprising: a symmetrical, bipolar, bilateral transmission transistor comprising first and second emitter/collector terminals and a base terminal; a first controllable high impedance current source circuit connected to one of said emitter/collector terminals for selectively maintaining a first constant magnitude direct current signal in a circuit including said connected one of said emitter/collector terminals; a second controllable high impedance current source circuit for selectively supplying a second constant magnitude direct current signal; current regulating means comprising first and second terminals connected respectively to said base terminal and to said second current source circuit and comprising means for maintaining the base current of said transmission transistor equal in magnitude to said first constant current signal, said base current being of a magnitude sufficient to saturate said transmission transistor for a substantial range of a.c. signals supplied to said emitter/collector terminals; and means for generating signals for controlling said first and second current source circuits.

Claim 7

A semiconductor transmission circuit arrangement according to claim 3 wherein said second constant magnitude direct current signal is equal in magnitude to said first constant current signal.

Claim 8

A semiconductor transmission circuit arrangement according to claim 3 wherein said first and second controllable high impedance direct current source circuits each comprise a collector of a single multiple collector transistor.

Claim 9

A semiconductor transmission circuit arrangement comprising: a PNP transmission comprising a base and first and second emitter/collector electrodes, said transistor constructed such that the electrical performances of said emitter/collector electrodes are identical; a controllable PNP constant direct current source transistor having an emitter, a base, and a plurality of collectors, said current source transistor constructed such that said collectors have substantially identical electrical operating characteristics, one of said collectors connected to one of said emitter/collector electrodes; means for generating signals for selectively controlling said current source transistor; and a current control circuit arrangement comprising first and second input terminals connected respectively to another of said collectors of said current source transistor and to said base of said transmission transistor, and means for controlling the current flowing from said base of said transmission transistor to be substantially equal in magnitude to the current flowing from said another collector.

Claim 10

A semiconductor transmission circuit arrangement comprising: a PNP transmission comprising a base and first and second emitter/collector electrodes, said transistor constructed such that the electrical performances of said emitter/collector electrodes are identical; a controllable PNP constant direct current source transistor having an emitter, a base, and a plurality of collectors, said current source transistor constructed such that said collectors have substantially identical electrical operating characteristics, one of said collectors connected to one of said emitter/collector electrodes; means for generating signals for selectively controlling said current source transistor; and a current control circuit arrangement comprising first and second input terminals connected respectively to another of said collectors of said current source transistor and to said base of said transmission transistor, and means for controlling the current flowing from said base of said transmission transistor to be substantially equal in magnitude to the current flowing from said another collector.

Claim 11

A semiconductor transmission circuit arrangement in accordance with claim 6 wherein a further one of said collectors of said controllabe PNP current source transistor is directly connected to the base of said current source transistor.

Claim 12

A semiconductor transmission circuit arrangement in accordance with claim 6 wherein said current control circuit arrangement comprises a voltage input terminal, first and second NPN transistors constructed to have substantially identical electrical operating characteristics, the collector of said first transistor connected to the base thereof, the base of said second NPN transistor and to said first input terminal, the collector of said second transistor connected to said second input terminal and the emitters of said first and second transistors coupled to said third input terminal.