Communication protocol between master and slave device with register information sharing

Claim 3

The method of claim 1, wherein the step of the slave device providing the status information comprises the step of the slave device providing the status information to the master device over the SPI during the first clock cycle following transmission of the communication initiation signal.

Claim 4

The method of claim 1, further comprising, prior to the step of the slave device providing the status information, the steps of: the slave device monitoring sources of events in the electronic device; and the slave device updating the status register with the status information in response to occurrence of the events.

Claim 7

The method in accordance with claim 4, further comprising the step of: the master device, substantially coincident with transmission of the portion of the updated register information by the slave device, providing to the slave device meaningless information that does not request specific interrupt information, that does not address the status register, and to which the slave device does not respond.

Claim 8

The method in accordance with claim 5, further comprising the step of: the master device responding, subsequent to receiving the portion of the register information, to the portion of the register information provided by the slave device.

Claim 9

The method in accordance with claim 4, further comprising the step of: the slave device, prior to receiving the communication initiation signal from the master device, requesting communication with the master device over the SPI.

Claim 10

The method in accordance with claim 4, wherein: the step of the master device providing the communication initiation signal comprises the step of the master device taking a slave select line of the SPI low; and the step of the slave device providing the portion of the updated register information comprises the step of transmitting the updated register information over a master-in-slave-out line of the SPI.

Claim 11

The method in accordance with claim 4, wherein the step of the slave device updating register information comprises the steps of: the slave device monitoring sources of events occurring in the electronic device; and the slave device storing status information about the events as the updated register information in the status register.

Claim 12

In a selective call receiver, a method for full duplex data transference between a microprocessor and a slave device included within the selective call receiver and coupled by a serial peripheral interface (SPI), the method comprising the steps of: the slave device monitoring sources of events in the selective call receiver; the slave device updating status information contained in a status register in response to at least one of the events occurring within the selective call receiver; the slave device providing an interrupt signal to the microprocessor over the SPI in response to updating the status information; the microprocessor, in response to the interrupt signal, providing a communication initiation signal to the slave device over the SPI, wherein the communication initiation signal addresses no registers of the slave device; and the slave device, in response to the communication initiation signal and during the first clock cycle following transmission of the communication initiation signal, automatically providing a portion of the status information contained in the status register to the microprocessor over the SPI without first receiving an address of the status register from the microprocessor.

Claim 13

In a selective call receiver, a method for full duplex data transference between a microprocessor and a slave device included within the selective call receiver and coupled by a serial peripheral interface (SPI), the method comprising the steps of: the slave device monitoring sources of events in the selective call receiver; the slave device updating status information contained in a status register in response to at least one of the events occurring within the selective call receiver; the slave device providing an interrupt signal to the microprocessor over the SPI in response to updating the status information; the microprocessor, in response to the interrupt signal, providing a communication initiation signal to the slave device over the SPI, wherein the communication initiation signal addresses no registers of the slave device; and the slave device, in response to the communication initiation signal and during the first clock cycle following transmission of the communication initiation signal, automatically providing a portion of the status information contained in the status register to the microprocessor over the SPI without first receiving an address of the status register from the microprocessor.

Claim 14

The method in accordance with claim 10, further comprising the step of: the microprocessor providing to the slave device meaningless information to which the slave device does not respond, wherein the meaningless information is provided over the SPI during the first clock cycle following transmission of the communication initiation signal.

Claim 15

The method in accordance with claim 10, wherein: the step of the microprocessor providing the communication initiation signal comprises the step of the microprocessor taking a slave select line of the SPI low; and the step of the slave device providing the portion of the status information includes the step of the slave device providing the portion of the status information over a master-in-slave-out line of the SPI.

Claim 16

An electronic device having full duplex data transference between semiconductor devices, comprising: a master device for providing to a slave device a communication initiation signal that addresses no registers included in the slave device; a serial peripheral interface (SPI) for coupling the master device to the slave device to provide the communication initiation signal thereover; and the slave device, comprising: means for receiving information signals from sources; a status register for storing information; means for updating the information stored in the status register in response to the information signals; and means for automatically providing the updated information to the master device over the SPI in response to the communication initiation signal without first receiving an address of the status register from the master device, wherein the updated information is provided by the slave device during the first clock cycle following the communication initiation signal.

Claim 17

An electronic device having full duplex data transference between semiconductor devices, comprising: a master device for providing to a slave device a communication initiation signal that addresses no registers included in the slave device; a serial peripheral interface (SPI) for coupling the master device to the slave device to provide the communication initiation signal thereover; and the slave device, comprising: means for receiving information signals from sources; a status register for storing information; means for updating the information stored in the status register in response to the information signals; and means for automatically providing the updated information to the master device over the SPI in response to the communication initiation signal without first receiving an address of the status register from the master device, wherein the updated information is provided by the slave device during the first clock cycle following the communication initiation signal.

Claim 18

The electronic device in accordance with claim 13, wherein the SPI further comprises a clock signal line for controlling data transference such that data transference between the master device and the slave device begins on a first falling edge of the clock signal after the communication initiation signal has been provided.

Claim 19

The electronic device in accordance with claim 13, wherein the master device comprises means for transmitting, over the SPI and at substantially the same time as the slave device provides the updated information over the SPI, meaningless information that does not address the status register and to which the slave device does not respond.

Claim 20

The electronic device in accordance with claim 15, wherein the SPI includes: a slave select line that is taken low by the master device to provide the communication initiation signal; a master-in-slave-out line for transferring the updated information to the master device; and a master-out-slave-in line for transferring the meaningless information to the slave device.

Claim 21

A selective call receiver having full duplex data communication between semiconductor devices, comprising: a microprocessor for providing a communication initiation signal that addresses no registers included in any other device of the selective call receiver; a support chip coupled to the microprocessor for receiving the communication initiation signal, for receiving interrupt signals from interrupt sources, for storing interrupt information corresponding to the interrupt signals in a register, and for automatically providing, in response to the communication initiation signal, portion of the interrupt information included in the register to the microprocessor without first receiving an address of the register from the microprocessor; and a serial peripheral interface (SPI) coupled between the microprocessor and the support chip for providing the communication initiation signal from the microprocessor to the support chip, for transferring the interrupt information from the support chip to the microprocessor, and for providing to the support chip, as a function of full duplex data transference between the support chip and the microprocessor, meaningless information to which the support chip does not respond, wherein the meaningless information does not address the register, and wherein the transference of both the meaningless information and the interrupt information occurs during the first clock cycle following the communication initiation signal.

Claim 22

A selective call receiver having full duplex data communication between semiconductor devices, comprising: a microprocessor for providing a communication initiation signal that addresses no registers included in any other device of the selective call receiver; a support chip coupled to the microprocessor for receiving the communication initiation signal, for receiving interrupt signals from interrupt sources, for storing interrupt information corresponding to the interrupt signals in a register, and for automatically providing, in response to the communication initiation signal, portion of the interrupt information included in the register to the microprocessor without first receiving an address of the register from the microprocessor; and a serial peripheral interface (SPI) coupled between the microprocessor and the support chip for providing the communication initiation signal from the microprocessor to the support chip, for transferring the interrupt information from the support chip to the microprocessor, and for providing to the support chip, as a function of full duplex data transference between the support chip and the microprocessor, meaningless information to which the support chip does not respond, wherein the meaningless information does not address the register, and wherein the transference of both the meaningless information and the interrupt information occurs during the first clock cycle following the communication initiation signal.