Patent US5630141A successfully refreshed from Google Patents.
US5630141A
Expired / Lapsed
US
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Hierarchical apparatus and method for processing device interrupts in a computer system
Assignee: Apple Inc
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Filing: 1996-03-07
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Granted: 1997-05-13
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Expires: 2016-03-07
Abstract
Abstract A method and apparatus for an innovative hardware independent interface to the external world. The interrupt services are part of an overall I/O model providing an object base I/O system that supports dynamic configuration of the system. The design of these interrupt exploit the advantages of Object Oriented Design (OOD) in an otherwise disorderly world of I/O. Object processing is designed into the architecture at the lowest level routines in the preferred embodiment of the invention. This includes an object oriented design all the way down to interrupt processing abstractions. These interrupt abstractions provide an architecturally sound framework for the dynamic installation, configuration, and timely execution of interrupt handlers.
Inventors
- 👤 Patrick D. Ross
- 👤 George W. Norman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 11:01
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/48; G06F9/4806; G06F9/4812; G06F9/52
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
230 words
An apparatus for providing interrupt processing utilizing interrupt management means for distributing interrupts to interrupt handlers for a plurality of devices connected together in a multi-level branching hardware hierarchy having a root level device and at least one other level having a plurality of leaf level devices in a computer system, the apparatus comprising: (a) a plurality of interrupt handlers connected together in a multi-level branching software hierarchy having a root level interrupt handler corresponding to said root level device and a plurality of leaf level interrupt handlers, each of said plurality of leaf level interrupt handlers corresponding to one of said plurality of leaf lever devices: (b) processing means in one of said interrupt handlers at a first level in said software hierarchy for determining a device interrupt state; (c) a first interrupt handler dispatch means in said one interrupt handler for analyzing said device interrupt state and initiating one of said plurality of interrupt handlers at a second level lower than said first level in said software hierarchy for each of said plurality of devices which is generating an interrupt at the corresponding level in the hardware hierarchy; (d) means in each of said initiated second level interrupt handlers for servicing said device interrupt state; and (e) processing means for passing information from each of said initiated second level interrupt handlers to an application to complete interrupt notification.
Claim 2
Independent Claim
230 words
An apparatus for providing interrupt processing utilizing interrupt management means for distributing interrupts to interrupt handlers for a plurality of devices connected together in a multi-level branching hardware hierarchy having a root level device and at least one other level having a plurality of leaf level devices in a computer system, the apparatus comprising: (a) a plurality of interrupt handlers connected together in a multi-level branching software hierarchy having a root level interrupt handler corresponding to said root level device and a plurality of leaf level interrupt handlers, each of said plurality of leaf level interrupt handlers corresponding to one of said plurality of leaf lever devices: (b) processing means in one of said interrupt handlers at a first level in said software hierarchy for determining a device interrupt state; (c) a first interrupt handler dispatch means in said one interrupt handler for analyzing said device interrupt state and initiating one of said plurality of interrupt handlers at a second level lower than said first level in said software hierarchy for each of said plurality of devices which is generating an interrupt at the corresponding level in the hardware hierarchy; (d) means in each of said initiated second level interrupt handlers for servicing said device interrupt state; and (e) processing means for passing information from each of said initiated second level interrupt handlers to an application to complete interrupt notification.
Claim 3
Dependent Claim
52 words
An apparatus for providing interrupt processing as recited in claim 1, wherein one or more of said interrupt handlers can appear on more than one level of said software hierarchy to reuse said one or more of said interrupt handlers for handling a device interrupt from one or more of said devices.
Claim 4
Dependent Claim
18 words
An apparatus for providing interrupt processing as recited in claim 1, including processing means to support nested interrupts.
Claim 5
Dependent Claim
19 words
An apparatus for providing interrupt processing as recited in claim 1, including processing means for supporting multiple programming languages.
Claim 6
Dependent Claim
20 words
An apparatus for providing interrupt processing as recited in claim 1, including processing means to maximally reuse existing interrupt handlers.
Claim 7
Dependent Claim
19 words
An apparatus for providing interrupt processing as recited in claim 1, including processing means to support multi-function card interrupts.
Claim 8
Dependent Claim
26 words
An apparatus for providing interrupt processing as recited in claim 1, including processing means for handling recursive interrupts employing one or more of said interrupt handlers.
Claim 9
Dependent Claim
23 words
An apparatus for providing interrupt processing as recited in claim 1, including processing means for independent development of each of said interrupt handlers.
Claim 10
Independent Claim
219 words
A method for providing interrupt processing, utilizing interrupt management means for distributing interrupts to interrupt handlers for a plurality of devices connected together in a multi-level branching hardware hierarchy having a root level device and at least one other level having a plurality of leaf level devices in a computer system, the method comprising the steps of: (a) creating a multi-level branching software hierarchy having a plurality of interrupt handlers connected together with a root level interrupt handler corresponding to said root level device add a plurality of leaf level interrupt handlers, each of said plurality of leaf level interrupt handlers corresponding to one of said plurality of leaf level devices; (b) determining a device interrupt state by means of one of said interrupt handlers at a first level in said software hierarchy; (c) analyzing said device interrupt state in said one interrupt handier and initiating one of said plurality of interrupt handlers at a second level lower than said first level in said software hierarchy for each of said plurality of devices which is generating an interrupt at the corresponding level in the hardware hierarchy; (d) said device interrupt state in each of said initiated second level interrupt handlers; and (e) passing information to an application from each said second level interrupt handlers to complete the interrupt notification.
Claim 11
Independent Claim
219 words
A method for providing interrupt processing, utilizing interrupt management means for distributing interrupts to interrupt handlers for a plurality of devices connected together in a multi-level branching hardware hierarchy having a root level device and at least one other level having a plurality of leaf level devices in a computer system, the method comprising the steps of: (a) creating a multi-level branching software hierarchy having a plurality of interrupt handlers connected together with a root level interrupt handler corresponding to said root level device add a plurality of leaf level interrupt handlers, each of said plurality of leaf level interrupt handlers corresponding to one of said plurality of leaf level devices; (b) determining a device interrupt state by means of one of said interrupt handlers at a first level in said software hierarchy; (c) analyzing said device interrupt state in said one interrupt handier and initiating one of said plurality of interrupt handlers at a second level lower than said first level in said software hierarchy for each of said plurality of devices which is generating an interrupt at the corresponding level in the hardware hierarchy; (d) said device interrupt state in each of said initiated second level interrupt handlers; and (e) passing information to an application from each said second level interrupt handlers to complete the interrupt notification.
Claim 12
Dependent Claim
56 words
A method for providing interrupt processing as recited in claim 9, wherein one or more of said interrupt handlers can appear on more than one level of said software hierarchy and the method further comprises: reusing one or more of said interrupt handlers for handling said device interrupt state from one or more of said devices.
Claim 13
Dependent Claim
16 words
A method for providing interrupt processing as recited in claim 9, further comprising: supporting nested interrupts.
Claim 14
Dependent Claim
17 words
A method for providing interrupt processing as recited in claim 9, further comprising: supporting multiple programming languages.
Claim 15
Dependent Claim
19 words
A method for providing interrupt processing as recited in claim 9, further comprising: maximizing reusability of existing interrupt handlers.
Claim 16
Dependent Claim
17 words
A method for providing interrupt processing as recited in claim 9, further comprising: supporting multi-function card interrupts.
Claim 17
Dependent Claim
24 words
A method for providing interrupt processing as recited in claim 9, further comprising: handling recursive interrupts employing one or more of said interrupt handlers.
Claim 18
Dependent Claim
17 words
A method for providing interrupt processing as recited in claim 9, further comprising: developing independent interrupt handlers.
Claim 19
Dependent Claim
18 words
An apparatus as recited in claim 1, wherein a plurality of processors and their associated interrupts are handled.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-05-12 | 2000-11-11 | 2001-05-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-05-12 | 2004-11-11 | 2005-05-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-05-12 | 2008-11-11 | 2009-05-13 | $7700.00 | Window Closed / Lapsed |