US5629876A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for interim in-situ testing of an electronic system with an inchoate ASIC
Assignee: LSI Corp
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Filing: 1992-08-31
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Granted: 1997-05-13
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Expires: 2012-08-31
Abstract
Abstract A technique is described for testing the performance of a target electronic system ultimately employing an ASIC comprising a core cell and surrounding logic, using an inchoate (designed, but not yet fabricated) ASIC on an interim basis. In one embodiment, a Q-part, or qualification part, which is essentially a bond-out of the core cell, is used in conjunction with programmable logic devices configured to perform the function of the surrounding logic. The Q-part and programmable logic are interconnected on a pod, and plugged into an interim version of a target electronic system. In another embodiment, the Q-part is software-simulated and interconnected on the pod to programmable logic devices. The programmable logic devices may be programmed either on-pod or off-pod, and signals incident to the operation of the pod plugged into the interim electronic system can be monitored and controlled.
Inventors
- 👤 Jen-Hsun Huang
- 👤 Michael D. Rostoker
- 👤 David Gluss
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 18:14
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/261; G06F30/00; G06F30/30; G06F30/32; G06F30/33
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
234 words
A method of emulating an electronic system for functional testing; the electronic system including a support member, a system device formed on the support member, a first connector that is formed on the support member and operatively connected to the system device, and a core-cell based Application Specific Integrated Circuit (ASIC) that interconnects with the first connector; the ASIC comprising a core-cell, and electronic core devices that are operatively connected to the core-cell; the method comprising the steps of: (a) constructing and operatively interconnecting the support member, system device and first connector; (b) constructing a test pod to include a Field-Programmable Circuit Board (FPCB), a Field-Programmable Interconnect (FPIC) that is mounted on the FPCB, a core unit that is mounted on the FPCB and is substantially functionally equivalent to the core-cell, programmable logic devices that are mounted on the FPCB, and a second connector that is mounted on the FPCB and interconnects with the first connector; (c) programming the FPIC to operatively interconnect the core unit, logic devices, and second connector via the FPCB; and programming the logic devices such that they are substantially functionally equivalent to core devices; such that the test pod is substantially functionally equivalent to the ASIC; (d) interconnecting the first and second connectors such that the support member, system device and test pod emulate the electronic system; and (e) functionally testing the support member, system device and test pod.
Claim 2
Independent Claim
234 words
A method of emulating an electronic system for functional testing; the electronic system including a support member, a system device formed on the support member, a first connector that is formed on the support member and operatively connected to the system device, and a core-cell based Application Specific Integrated Circuit (ASIC) that interconnects with the first connector; the ASIC comprising a core-cell, and electronic core devices that are operatively connected to the core-cell; the method comprising the steps of: (a) constructing and operatively interconnecting the support member, system device and first connector; (b) constructing a test pod to include a Field-Programmable Circuit Board (FPCB), a Field-Programmable Interconnect (FPIC) that is mounted on the FPCB, a core unit that is mounted on the FPCB and is substantially functionally equivalent to the core-cell, programmable logic devices that are mounted on the FPCB, and a second connector that is mounted on the FPCB and interconnects with the first connector; (c) programming the FPIC to operatively interconnect the core unit, logic devices, and second connector via the FPCB; and programming the logic devices such that they are substantially functionally equivalent to core devices; such that the test pod is substantially functionally equivalent to the ASIC; (d) interconnecting the first and second connectors such that the support member, system device and test pod emulate the electronic system; and (e) functionally testing the support member, system device and test pod.
Claim 3
Dependent Claim
25 words
A method as in claim 1, in which step (b) comprises constructing the test pod such that the core unit is a hardware logic unit.
Claim 4
Dependent Claim
36 words
A method as in claim 1, in which: step (b) comprises constructing the test pod such that the core unit is a software programmable logic unit; and step (c) further comprises software programming the logic unit.
Claim 5
Dependent Claim
84 words
A method as in claim 1 in which: step (b) comprises the substeps of: (b1) providing the FPCB as being formed with an array of holes, and a routing grid that connects to said holes; (b2) mounting the FPIC on the FPCB in such a manner as to programmably interconnect said holes through the routing grid; and (b3) mounting the core unit and logic devices on the FPCB such that terminals of the core unit and logic devices are connected to said holes respectively.
Claim 6
Dependent Claim
44 words
A method as in claim 1, in which: step (b) further comprises constructing the test pod as including a third connector for external connection; and step (c) further comprises operatively interconnecting the core unit and the logic devices in circuit to the third connector.
Claim 7
Dependent Claim
23 words
A method as in claim 5, in which step (e) comprises sensing electrical signals generated by the core unit through the third connector.
Claim 8
Dependent Claim
23 words
A method as in claim 5, in which step (e) comprises sensing electrical signals generated by the logic devices through the third connector.
Claim 9
Dependent Claim
40 words
A method as in claim 5, in which: step (b) comprises constructing the test pod such that the core unit is a software programmable logic unit; and step (c) further comprises software programming the logic unit through the third connector.
Claim 10
Dependent Claim
40 words
A method as in claim 5, in which: step (c) further comprises programming the logic devices to pass test signals between the core unit and the third connector; and step (e) comprises passing said test signals through the third connector.
Claim 11
Dependent Claim
45 words
A method as in claim 5, in which step (e) comprises the substeps of: (e1) connecting a test apparatus to the third connector; and (e2) passing test signals between the test apparatus and the support member, system device and test pod through the third connector.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-05-12 | 2000-11-11 | 2001-05-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-05-12 | 2004-11-11 | 2005-05-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-05-12 | 2008-11-11 | 2009-05-13 | $7700.00 | Window Closed / Lapsed |