Self-biased phase-locked loop

Claim 2

A current controlled semiconductor device, wherein said current controlled semiconductor device is biased with a bias current, said device comprising: a) a first feedback path, said first feedback path dynamically controlling an output of said current controlled semiconductor device with a control current; and b) a second feedback path, said second feedback path including a bias loop, said bias loop determining the magnitude of said control current and thereby providing said bias current in response to said control current.

Claim 3

The device of claim 1 wherein said bias loop comprises a first current mirror and a second current mirror, and wherein said bias loop determines the magnitude of said control current by mirroring said control current to said bias current.

Claim 4

The device of claim 2 wherein said first and second current mirrors comprise field effect transistors.

Claim 5

The device of claim 2 wherein said first current mirror comprises N-channel field effect transistors and wherein said second current mirror comprises P-channel field effect transistors.

Claim 6

The device of claim 1 wherein said bias loop has substantially unity gain.

Claim 7

The device of claim 1 wherein said semiconductor device is a phase-locked loop.

Claim 8

The apparatus of claim 1 wherein said semiconductor device is a phase-locked loop and including a current controlled oscillator within said phase-locked loop which is supplied bias current by said bias loop.

Claim 9

The device of claim 1 further comprising a start up mechanism, said start-up mechanism including a current mirror, said current mirror effecting a start-up current in said bias loop on power-up of said current controlled semiconductor device.

Claim 10

The device of claim 1 wherein said bias current tracks said control current.

Claim 11

A self-biased current controlled oscillator in a phase-locked loop, wherein said current controlled oscillator generates an output signal with a frequency proportional to an input current, wherein said input current includes the sum of a bias current and a control current and wherein said control current is supplied by said phase-locked loop, said current controlled oscillator comprising: a) a first current mirror, said first current mirror sinking said input current; b) a second current mirror forming a feedback loop with said first current mirror, said feedback loop providing said bias current to said current controlled oscillator, wherein said bias current tracks said input current.

Claim 12

A self-biased current controlled oscillator in a phase-locked loop, wherein said current controlled oscillator generates an output signal with a frequency proportional to an input current, wherein said input current includes the sum of a bias current and a control current and wherein said control current is supplied by said phase-locked loop, said current controlled oscillator comprising: a) a first current mirror, said first current mirror sinking said input current; b) a second current mirror forming a feedback loop with said first current mirror, said feedback loop providing said bias current to said current controlled oscillator, wherein said bias current tracks said input current.

Claim 13

The current controlled oscillator of claim 10 wherein said first and second current mirrors comprise field effect transistors.

Claim 14

The current controlled oscillator of claim 10 wherein said feedback loop has substantially positive unity gain.

Claim 15

The current controlled oscillator of claim 10 wherein said first current mirror comprises N-channel field effect transistors and wherein said second current mirror comprises P-channel field effect transistors.

Claim 16

The current controlled oscillator of claim 10 further comprising a start up mechanism, said start-up mechanism including a third current mirror, said third current mirror effecting a start-up current in said bias loop on power-up of said self-biased current controlled oscillator.

Claim 17

A self-biased phase-locked loop, wherein said phase-locked loop includes a current controlled oscillator, a voltage-to-current converter and a charge pump, wherein said current controlled oscillator generates an output signal with a frequency proportional to an input current, the self-biased phase-locked loop comprising: a) a first current mirror, said first current mirror mirroring a current responsive to said input current; b) a second current mirror forming a feedback loop with said first current mirror, said feedback loop having substantially unity gain and providing a first bias current to said current controlled oscillator which is dynamically controlled by said feedback loop to track said input current; c) a third current mirror, said third current mirror supplying a second bias current to said voltage-to-current converter that is proportional to said first bias current; d) a fourth current mirror, said fourth current mirror supplying a third bias current to said charge pump that is proportional to said first bias current of said current controlled oscillator; e) a start-up mechanism, said start-up mechanism supplying a start-up current to said second current mirror on power up of said phase-locked loop, said start-up mechanism turning off said start-up current when said first bias current is established.

Claim 18

A self-biased phase-locked loop, wherein said phase-locked loop includes a current controlled oscillator, a voltage-to-current converter and a charge pump, wherein said current controlled oscillator generates an output signal with a frequency proportional to an input current, the self-biased phase-locked loop comprising: a) a first current mirror, said first current mirror mirroring a current responsive to said input current; b) a second current mirror forming a feedback loop with said first current mirror, said feedback loop having substantially unity gain and providing a first bias current to said current controlled oscillator which is dynamically controlled by said feedback loop to track said input current; c) a third current mirror, said third current mirror supplying a second bias current to said voltage-to-current converter that is proportional to said first bias current; d) a fourth current mirror, said fourth current mirror supplying a third bias current to said charge pump that is proportional to said first bias current of said current controlled oscillator; e) a start-up mechanism, said start-up mechanism supplying a start-up current to said second current mirror on power up of said phase-locked loop, said start-up mechanism turning off said start-up current when said first bias current is established.

Claim 19

The self-biased phase-locked loop of claim 15 wherein said first and second current mirrors comprise field effect transistors.

Claim 20

The self-biased phase-locked loop of claim 15 wherein said first current mirror comprises N-channel field effect transistors and wherein said second current mirror comprises P-channel field effect transistors.

Claim 23

The method of claim 18 wherein the step of mirroring back said input current along a feedback bias loop comprises mirroring back along a feedback bias loop with substantially unity gain.

Claim 24

The method of claim 18 wherein said current controlled device comprises a current controlled oscillator.

Claim 25

The method of claim 18 wherein the step of providing said input current to said current controlled device is performed by a phase-locked loop.