US4494080A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Voltage-controlled oscillator with independent gain and frequency controls
Assignee: International Business Machines Corp
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Filing: 1981-11-16
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Granted: 1985-01-15
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Expires: 2001-11-16
Abstract
Abstract A voltage-controlled oscillator (VCO) comprises a current controlled oscillator (ICO) and control circuitry which independently adjusts the gain (K v ) and free-run or center frequency of the VCO. The control circuitry includes a first current source selected to set the free-run frequency of the VCO and a second current source selected to set the gain (K v ) of the VCO. The current sources are coupled to a common node in a summing/difference configuration. The controlled current generated from the summing/difference configuration is delivered into the ICO. Independent current mirrors are utilized to supply controlled current into the node of the summing/difference configuration.
Inventors
- 👤 Mark G. Call
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 16:23
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/099
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
244 words
An improved phase-locked loop comprising: comparator means for comparing a first and a second signal, wherein said first signal is a signal for establishing a phase standard, for generating an error signal indicative of any phase difference between said first and second signals; filter means having an input coupled to receive the error signal from said comparator means for generating a first control signal; a first circuit means for generating a second control signal, said first circuit means including: (a) a supply voltage source having first and second terminals; (b) a current mirror circuit means coupled to one of said voltage source terminals and having an output for supplying said second control signal; and (c) a resistor coupling the input of said current mirror circuit means to the other of said voltage source terminals; an oscillator for producing an output signal with a frequency and gain determined by an input signal thereto; means for deriving said second signal for said comparator means from said oscillator output signal; a second circuit means responsive to said first control signal from said filter means for selectively producing a third control signal for controlling the gain of said oscillator; means combining said second and third control signals into a summing/difference signal; and means for deriving the input signal to said oscillator from said summing/difference signal whereby said phase-locked loop has its free-run frequency set by the first circuit means and the gain set by the second circuit means.
Claim 2
Dependent Claim
244 words
An improved phase-locked loop comprising: comparator means for comparing a first and a second signal, wherein said first signal is a signal for establishing a phase standard, for generating an error signal indicative of any phase difference between said first and second signals; filter means having an input coupled to receive the error signal from said comparator means for generating a first control signal; a first circuit means for generating a second control signal, said first circuit means including: (a) a supply voltage source having first and second terminals; (b) a current mirror circuit means coupled to one of said voltage source terminals and having an output for supplying said second control signal; and (c) a resistor coupling the input of said current mirror circuit means to the other of said voltage source terminals; an oscillator for producing an output signal with a frequency and gain determined by an input signal thereto; means for deriving said second signal for said comparator means from said oscillator output signal; a second circuit means responsive to said first control signal from said filter means for selectively producing a third control signal for controlling the gain of said oscillator; means combining said second and third control signals into a summing/difference signal; and means for deriving the input signal to said oscillator from said summing/difference signal whereby said phase-locked loop has its free-run frequency set by the first circuit means and the gain set by the second circuit means.
Claim 3
Dependent Claim
26 words
The improved phase-lock loop of claim 1 wherein the resistor is of a value selected to set the free-run frequency (F FR ) of the oscillator.
Claim 4
Dependent Claim
229 words
An improved phase-locked loop comprising: comparator means for comparing a first and a second signal, wherein said first signal is a reference frequency signal, and for generating an error signal indicative of any phase difference between said first and second signals; filter means having an input coupled to receive the error signal from said comparator means for generating a first control signal; a first circuit means responsive to a reference control signal to generate a second control signal for establishing the free-run frequency of the loop; an oscillator for producing an output signal with a frequency and gain determined by an input signal thereto; means for deriving said second signal for said comparator means from said oscillator output signal; a second circuit means responsive to said first control signal from said filter means for selectively producing a third control signal, the second circuit means including: (a) a supply voltage source; and (b) a first current mirror connected to said supply voltage source, having an input connected to said first control signal and having an output for supplying said third control signal; means combining said second and third control signal into a summing/difference signal; and means deriving the input signal to said oscillator from said summing/difference signal whereby said phase-locked loop has its free-run frequency set by the first circuit means, and the gain set by the second circuit means.
Claim 5
Dependent Claim
229 words
An improved phase-locked loop comprising: comparator means for comparing a first and a second signal, wherein said first signal is a reference frequency signal, and for generating an error signal indicative of any phase difference between said first and second signals; filter means having an input coupled to receive the error signal from said comparator means for generating a first control signal; a first circuit means responsive to a reference control signal to generate a second control signal for establishing the free-run frequency of the loop; an oscillator for producing an output signal with a frequency and gain determined by an input signal thereto; means for deriving said second signal for said comparator means from said oscillator output signal; a second circuit means responsive to said first control signal from said filter means for selectively producing a third control signal, the second circuit means including: (a) a supply voltage source; and (b) a first current mirror connected to said supply voltage source, having an input connected to said first control signal and having an output for supplying said third control signal; means combining said second and third control signal into a summing/difference signal; and means deriving the input signal to said oscillator from said summing/difference signal whereby said phase-locked loop has its free-run frequency set by the first circuit means, and the gain set by the second circuit means.
Claim 6
Dependent Claim
56 words
An improved phase-locked loop in accordance with clai 3 wherein said first circuit means includes: (a) a second current mirror connected to said supply voltage source; and (b) means deriving the input for said second current mirror from said reference control signal for producing said second control signal as the output of said second current mirror.
Claim 7
Dependent Claim
56 words
An improved phase-locked loop in accordance with clai 3 wherein said first circuit means includes: (a) a second current mirror connected to said supply voltage source; and (b) means deriving the input for said second current mirror from said reference control signal for producing said second control signal as the output of said second current mirror.
Claim 8
Dependent Claim
124 words
An improved phase-locked loop (PLL) module comprising: an integrated section of said module including: a phase comparator; a loop filter connected to the output of the phase comparator; a current-controlled oscillator having its output coupled to an input of the phase comparator; a first current mirror means; a second current mirror means; said first and second current mirror means coupled in a summing/difference configuration to generate a controlled signal to drive the oscillator; and a nonintegrated section including a pair of electrical circuits, one of which is coupled to the input of said first current mirror means to set the gain K v and the other of which is coupled to said second current mirror means to set the center frequency of the oscillator.
Claim 9
Dependent Claim
124 words
An improved phase-locked loop (PLL) module comprising: an integrated section of said module including: a phase comparator; a loop filter connected to the output of the phase comparator; a current-controlled oscillator having its output coupled to an input of the phase comparator; a first current mirror means; a second current mirror means; said first and second current mirror means coupled in a summing/difference configuration to generate a controlled signal to drive the oscillator; and a nonintegrated section including a pair of electrical circuits, one of which is coupled to the input of said first current mirror means to set the gain K v and the other of which is coupled to said second current mirror means to set the center frequency of the oscillator.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-01-15 | 1988-07-16 | 1989-01-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-01-15 | 1992-07-16 | 1993-01-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-01-15 | 1996-07-16 | 1997-01-15 | $7700.00 | Window Closed / Lapsed |