Magnetic spin transistor device, logic gate & method of operation

Claim 2

A magnetic spin transistor device comprising: a first ferromagnetic layer having a first coercivity; a second ferromagnetic layer having a second coercivity smaller than said first coercivity; a paramagnetic layer situated between said first and second ferromagnetic layers, said paramagnetic layer having a thickness less than an electron spin diffusion length; an insulating layer situated over a portion of said second ferromagnetic layer; and a conductive write layer situated over a portion of said insulating layer for carrying a write electric current and inductively coupling a write magnetic field associated with said write current to said second ferromagnetic layer.

Claim 3

The spin transistor of claim 1, wherein both the first and second ferromagnetic layers are magnetically anisotropic.

Claim 4

The spin transistor of claim 1, further including a write current generator connected to said conductive write layer for generating said write current and said associated write magnetic field.

Claim 5

The device of claim 1, further including a 0.08 micron thin film of gold positioned over said first ferromagnetic layer, and wherein the first ferromagnetic layer is a 0.06 micron thin film of iron, cobalt or permalloy, said second ferromagnetic layer is a 0.06 micron thin film of iron, cobalt or permalloy, said paramagnetic layer is a 0.01 micron thin film of gold, copper or aluminum, said insulating layer is a 0.05 micron thin film of polyimide, silicon dioxide or aluminum oxide, and said conducting layer a 0.01 micron thin film of gold, copper or aluminum.

Claim 6

The spin transistor of claim 3, wherein said second ferromagnetic layer: (i) is set to a first magnetization state in response to a positive write current and associated positive write magnetic field; (ii) is set to a second magnetization state in response to a negative write current and associated negative write magnetic field; and (iii) does not change magnetization state in response to a zero write current and associated zero write magnetic field.

Claim 7

The spin transistor of claim 5, wherein the second ferromagnetic layer magnetization orientation is retained in said state until a different state is set in said layer.

Claim 8

The spin transistor of claim 1, further including an output signal from said second ferromagnetic layer, and wherein said output signal depends on the magnetization orientation state of said second ferromagnetic layer.

Claim 9

The spin transistor of claim 7, further including a bias electrical current input connected to said first ferromagnetic layer for reading the output signal.

Claim 10

The spin transistor of claim 1, wherein said transistor is used as a memory element.

Claim 11

The device of claim 9, wherein the two states of the magnetization orientation of said second ferromagnetic layer correspond to data values stored in said memory element.

Claim 12

The spin transistor of claim 1, further including a plurality of additional spin transistors coupled together in an array to form a spin transistor memory array.

Claim 13

A magnetic spin transistor logic gate device comprising: a magnetic spin transistor, said transistor having a first ferromagnetic layer with a first magnetization orientation state, a second ferromagnetic layer with a second magnetization orientation state, a paramagnetic layer, and an output; a conductive write line for inductively coupling said second ferromagnetic layer of said transistor to an input magnetic field associated with one or more input logic signals; and wherein the output of said spin transistor is a predetermined function of said magnetic field associated with said data input signals and said second magnetization orientation state.

Claim 14

A magnetic spin transistor logic gate device comprising: a magnetic spin transistor, said transistor having a first ferromagnetic layer with a first magnetization orientation state, a second ferromagnetic layer with a second magnetization orientation state, a paramagnetic layer, and an output; a conductive write line for inductively coupling said second ferromagnetic layer of said transistor to an input magnetic field associated with one or more input logic signals; and wherein the output of said spin transistor is a predetermined function of said magnetic field associated with said data input signals and said second magnetization orientation state.

Claim 15

The device of claim 12, wherein a coercivity value of the first ferromagnetic layer is greater than a coercivity value of the second ferromagnetic layer, and both layers are magnetically anisotropic.

Claim 16

The device of claim 12, wherein the input signals are output signals from one or more additional spin transistors.

Claim 17

The device of claim 12, wherein the logic gate implements the predetermined logical function of one of the following: an OR gate, a NOR gate, a NOT gate, a NAND gate, and an AND gate.

Claim 18

The device of claim 12, wherein the second initial magnetization orientation state is set to one of an up and a down condition based on the predetermined logical function being implemented by the logic gate.

Claim 19

The device of claim 12, wherein the amplitude of each current data input signal is set to one of a first value and a second value equal to twice said first value, based on the predetermined logical function being implemented by the logic gate.

Claim 20

The device of claim 12, wherein the second initial magnetization orientation state is set to a down condition, the current data input signals are set to said first value, and the spin transistor implements the predetermined logic function of an OR gate.

Claim 21

The device of claim 12, wherein the second initial magnetization orientation state is set to a down condition, the current data input signals are set to said second value, and the spin transistor implements the predetermined logic function of an AND gate.

Claim 22

The device of claim 12, wherein the second initial magnetization orientation state is set to an up condition, the current data input signals are set to said first value, and the spin transistor implements the predetermined logic function of an NOR gate.

Claim 23

The device of claim 20, wherein the second initial magnetization orientation state is set to an up condition, the current data input signals are set to said second value, and the spin transistor implements the predetermined logic function of an NAND gate.

Claim 24

The device of claim 20, wherein the second initial magnetization orientation state is set to an up condition and a single current data input signal is set to a first value, and the spin transistor implements the predetermined logic function of an NOT gate.

Claim 25

The device of claim 12, wherein the predetermined logical function implemented by said logic gate is changed by changing the second initial magnetization orientation state and the value of the input signal.

Claim 26

A logic gate device for implementing a logical function relating a combination of one or more input signals to an output signal comprising: a first ferromagnetic layer with a magnetization orientation with a fixed state, and a first coercivity; an input electrode connected to said first layer for receiving read current signals; a second ferromagnetic layer with a modifiable magnetization orientation, said orientation having at least a first and second state, and wherein said second layer has a second coercivity smaller than said first coercivity; an output electrode connected to said second layer for carrying an output signal; a paramagnetic layer situated between said first and second ferromagnetic layers, said paramagnetic layer having a thickness less than an electron spin diffusion length; a wire for inductively coupling said second ferromagnetic layer with a magnetic field generated by the combined current of the combination of one or more input data signals on said wire, said input data signals having either a first or second current value; said second ferromagnetic layer magnetization orientation state being modifiable only by magnetic fields exceeding a threshold field value corresponding to a combined threshold current value; wherein the spin transistor output signal is a first logical value when said second magnetization orientation state is modified by the combination of said input data signals, and said output signal is a second logical value when said second magnetization orientation state is not modified by said signals.

Claim 27

A logic gate device for implementing a logical function relating a combination of one or more input signals to an output signal comprising: a first ferromagnetic layer with a magnetization orientation with a fixed state, and a first coercivity; an input electrode connected to said first layer for receiving read current signals; a second ferromagnetic layer with a modifiable magnetization orientation, said orientation having at least a first and second state, and wherein said second layer has a second coercivity smaller than said first coercivity; an output electrode connected to said second layer for carrying an output signal; a paramagnetic layer situated between said first and second ferromagnetic layers, said paramagnetic layer having a thickness less than an electron spin diffusion length; a wire for inductively coupling said second ferromagnetic layer with a magnetic field generated by the combined current of the combination of one or more input data signals on said wire, said input data signals having either a first or second current value; said second ferromagnetic layer magnetization orientation state being modifiable only by magnetic fields exceeding a threshold field value corresponding to a combined threshold current value; wherein the spin transistor output signal is a first logical value when said second magnetization orientation state is modified by the combination of said input data signals, and said output signal is a second logical value when said second magnetization orientation state is not modified by said signals.

Claim 28

The device of claim 24, wherein the data input signals are output signals from one or more additional spin transistors.

Claim 29

The device of claim 24, wherein the output first logical value is a binary "1," and the second logical value is a binary "0."

Claim 30

The device of claim 24, wherein the spin transistor output signal is a function of the combination of input data signals corresponding to one of the following functions: an OR gate, a NOR gate, a NOT gate, a NAND gate, and an AND gate.

Claim 31

The device of claim 24, wherein the second initial magnetization orientation state is set to one of an up and a down condition based on the logical function being implemented by the logic gate.

Claim 32

The device of claim 24, wherein the value of each current data input signal is set to one of a first value and a second value equal to twice said first value, based on the logical function being implemented by the logic gate.

Claim 33

A magnetic spin transistor, said transistor having a transimpedance R S and further comprising: a ferromagnetic emitter; a ferromagnetic collector, wherein said ferromagnetic collector generates a current that is output to a load resistance R L ; a paramagnetic base situated between said first and second ferromagnetic layers, said paramagnetic base having a thickness less than an electron spin diffusion length, and a parasitic resistance value R B ; wherein a desired offset to said output current is provided by selecting appropriate values of R L , R S and R B .

Claim 34

A magnetic spin transistor, said transistor having a transimpedance R S and further comprising: a ferromagnetic emitter; a ferromagnetic collector, wherein said ferromagnetic collector generates a current that is output to a load resistance R L ; a paramagnetic base situated between said first and second ferromagnetic layers, said paramagnetic base having a thickness less than an electron spin diffusion length, and a parasitic resistance value R B ; wherein a desired offset to said output current is provided by selecting appropriate values of R L , R S and R B .

Claim 35

A magnetic spin transistor circuit comprising: a first magnetic spin transistor; and a second magnetic spin transistor, said first magnetic spin transistor being inductively coupled to said second magnetic spin transistor.

Claim 36

A magnetic spin transistor circuit comprising: a first magnetic spin transistor; and a second magnetic spin transistor, said first magnetic spin transistor being inductively coupled to said second magnetic spin transistor.

Claim 37

The circuit of claim 31, wherein the first spin transistor further includes a first input line and first output line, the second transistor includes a second input line and second output line, and the first output line is connected to the second input line.

Claim 38

The circuit of claim 31, wherein each spin transistor further includes a first ferromagnetic layer with a first magnetization state, a second ferromagnetic layer with a second magnetization state, and a paramagnetic layer situated between said first and second ferromagnetic layers, said paramagnetic layer having a thickness less than an electron spin diffusion length.

Claim 39

The circuit of claim 31, wherein said first ferromagnetic layer has a coercivity higher than said second ferromagnetic layer.

Claim 40

The circuit of claim 34, wherein said first and second ferromagnetic layers are magnetically anisotropic.

Claim 41

The circuit of claim 35, wherein the second ferromagnetic layer in the first and second spin transistors is patterned to have a first magnetization coercivity in the direction of their respective output lines, and a second larger magnetization coercivity in the direction of their respective input lines, such that the output current from the respective first and second outputs does not reorient the magnetization of the respective second ferromagnetic layers.

Claim 42

A magnetic spin transistor logic processing circuit comprising: a first magnetic spin transistor gate logic element, said first gate logic element including a first spin transistor with a first input and first output, said first input being inductively coupled to a data input line, and said output being connected to a data output line; and a second magnetic spin transistor gate logic element, said second gate logic element including a second spin transistor with a second input and second output, said second input being inductively coupled to the data output line from said first gate logic element, and said second output being connected to a second data output line.

Claim 43

A magnetic spin transistor logic processing circuit comprising: a first magnetic spin transistor gate logic element, said first gate logic element including a first spin transistor with a first input and first output, said first input being inductively coupled to a data input line, and said output being connected to a data output line; and a second magnetic spin transistor gate logic element, said second gate logic element including a second spin transistor with a second input and second output, said second input being inductively coupled to the data output line from said first gate logic element, and said second output being connected to a second data output line.

Claim 44

A magnetic spin transistor comprising: a first ferromagnetic layer having a first magnetization state; a second ferromagnetic layer having a second magnetization state and first and second magnetization axes, said second ferromagnetic layer further having an output for a spin transistor current output and being configured to inductively couple input current from an input line; a paramagnetic layer situated between said first and second layers; said magnetization axes of said second ferromagnetic layer being configured such that the magnetization state of said layer is not affected when the spin transistor output current is greater than the input current.

Claim 45

A magnetic spin transistor comprising: a first ferromagnetic layer having a first magnetization state; a second ferromagnetic layer having a second magnetization state and first and second magnetization axes, said second ferromagnetic layer further having an output for a spin transistor current output and being configured to inductively couple input current from an input line; a paramagnetic layer situated between said first and second layers; said magnetization axes of said second ferromagnetic layer being configured such that the magnetization state of said layer is not affected when the spin transistor output current is greater than the input current.

Claim 46

The spin transistor of claim 38, wherein said first ferromagnetic layer has a coercivity higher than said second ferromagnetic layer.

Claim 47

The circuit of claim 38, wherein said first and second ferromagnetic layers are magnetically anisotropic.

Claim 48

The spin transistor of claim 38, wherein the second ferromagnetic layer is patterned to have a first magnetization coercivity in the direction of the output line, and a second larger coercivity in the direction of the input line, such that the output current from the spin transistor does not reorient the magnetization of the second ferromagnetic layer.