Static memory cell and method of manufacturing a static memory cell

Claim 2

A static memory cell comprising: a semiconductor substrate of a first conductivity type; a buried layer in the substrate, the buried layer having a second conductivity type opposite to the first conductivity type, and the buried layer having an average dopant concentration of at least 1×10 19 ions/cm 3 ; a transistor formed relative to the substrate over the buried layer, the transistor having a channel of the second conductivity type, the transistor having a gate, the transistor having a memory node including an average dopant concentration of at least 1×10 19 ions/cm 3 , the memory node including a lowermost portion which is ≦0.1 micron above the buried layer, and the transistor having a digit line node having an average dopant concentration of at least 1×10 19 ions/cm 3 ; and a region in junction relation with the memory node and defining a tunnel diode between the region and the memory node, the region having an average dopant concentration of at least 1×10 19 ions/cm 3 .

Claim 3

A static memory cell comprising: a semiconductor substrate of a first conductivity type; a buried layer in the substrate, the buried layer having a second conductivity type opposite to the first conductivity type, and the buried layer having an average dopant concentration of at least 1×10 19 ions/cm 3 ; a transistor formed relative to the substrate over the buried layer, the transistor having a channel of the second conductivity type, and the transistor having a gate, a memory node having an average dopant concentration of at least 1×10 19 ions/cm 3 , and a digit line node having an average dopant concentration of at least 1×10 19 ions/cm 3 ; and a region in junction relation with the memory node and defining a tunnel diode between the region and the memory node, the region having an average dopant concentration of at least 1×10 19 ions/cm 3 , and the memory node including a lowermost portion which is ≦0.4 micron above the buried layer.

Claim 4

A static memory cell comprising: a semiconductor substrate of a first conductivity type; a buried layer in the substrate, the buried layer having a second conductivity type opposite to the first conductivity type, and the buried layer having an average dopant concentration of at least 1×10 19 ions/cm 3 ; a transistor formed relative to the substrate over the buried layer, the transistor having a channel of the second conductivity type, and the transistor having a gate, a memory node having an average dopant concentration of at least 1×10 19 ions/cm 3 , and a digit line node having an average dopant concentration of at least 1×10 19 ions/cm 3 ; and a region in junction relation with the memory node and defining a tunnel diode between the region and the memory node, the region having an average dopant concentration of at least 1×10 19 ions/cm 3 , and the memory node including a lowermost portion which is ≦0.4 micron above the buried layer.

Claim 5

A static memory cell comprising: a semiconductor substrate of a first conductivity type; a buried layer in the substrate, the buried layer having a second conductivity type opposite to the first conductivity type; a transistor formed relative to the substrate over the buried layer, the transistor having a source of the second conductivity type, a gate, and a drain of the second conductivity type, the source having a depth in the substrate greater than the depth of the drain and the source including a lowermost portion which is ≦0.4 micron above the buried layer; and a region in junction relation with the source, the region being of the first conductivity type.

Claim 6

A static memory cell comprising: a semiconductor substrate of a first conductivity type; a buried layer in the substrate, the buried layer having a second conductivity type opposite to the first conductivity type; a transistor formed relative to the substrate over the buried layer, the transistor having a source of the second conductivity type, a gate, and a drain of the second conductivity type, the source having a depth in the substrate greater than the depth of the drain and the source including a lowermost portion which is ≦0.4 micron above the buried layer; and a region in junction relation with the source, the region being of the first conductivity type.

Claim 7

A static memory cell comprising: a semiconductor substrate of a first conductivity type; a buried layer in the substrate, the buried layer having a second conductivity type opposite to the first conductivity type; a transistor formed relative to the substrate over the buried layer, the transistor having a source of the second conductivity type, a gate, and a drain of the second conductivity type, the source having a depth in the substrate greater than the depth of the drain and the source including a lowermost portion which is ≦0.1 micron above the buried layer; and a region in junction relation with the source, the region being of the first conductivity type.

Claim 8

A static memory cell comprising: a semiconductor substrate of a first conductivity type; a buried layer in the substrate, the buried layer having a second conductivity type opposite to the first conductivity type; a transistor formed relative to the substrate over the buried layer, the transistor having a source of the second conductivity type, a gate, and a drain of the second conductivity type, the source having a depth in the substrate greater than the depth of the drain and the source including a lowermost portion which is ≦0.1 micron above the buried layer; and a region in junction relation with the source, the region being of the first conductivity type.

Claim 9

A static memory cell comprising: a p-type semiconductor substrate having an average p-type dopant concentration of at least 1×10 16 ions/cm 3 and being connected to a first voltage; a buried n-type diffusion layer in the substrate, the n-type layer having an average n-type dopant concentration of at least 1×10 19 ions/cm 3 and being connected to a second voltage lower than the first voltage; an n-channel transistor formed relative to the substrate over the buried n-type layer, the n-channel transistor having a source, a gate, and a drain, the source having an average n-type dopant concentration of at least 1×10 19 ions/cm 3 and the source having a lowermost portion which is ≦0.4 micron above the n-type diffusion layer, and the drain having an average n-type dopant concentration of at least 1×10 19 ions/cm 3 ; and a p-type region in junction relation with the source and operating in combination with the source to define a tunnel diode, the p-type region being connected to a third voltage higher than the first voltage.

Claim 10

A static memory cell comprising: a p-type semiconductor substrate having an average p-type dopant concentration of at least 1×10 16 ions/cm 3 and being connected to a first voltage; a buried n-type diffusion layer in the substrate, the n-type layer having an average n-type dopant concentration of at least 1×10 19 ions/cm 3 and being connected to a second voltage lower than the first voltage; an n-channel transistor formed relative to the substrate over the buried n-type layer, the n-channel transistor having a source, a gate, and a drain, the source having an average n-type dopant concentration of at least 1×10 19 ions/cm 3 and the source having a lowermost portion which is ≦0.4 micron above the n-type diffusion layer, and the drain having an average n-type dopant concentration of at least 1×10 19 ions/cm 3 ; and a p-type region in junction relation with the source and operating in combination with the source to define a tunnel diode, the p-type region being connected to a third voltage higher than the first voltage.

Claim 11

A static memory cell comprising: a p-type semiconductor substrate having an average p-type dopant concentration of at least 1×10 16 ions/cm 3 and being connected to a first voltage; a buried n-type diffusion layer in the substrate, the n-type layer having an average n-type dopant concentration of at least 1×10 19 ions/cm 3 and being connected to a second voltage lower than the first voltage; an n-channel transistor formed relative to the substrate over the buried n-type layer, the n-channel transistor having a source, a gate, and a drain, the source having an average n-type dopant concentration of at least 1×10 19 ions/cm 3 and the source having a lowermost portion which is ≦0.1 micron above the n-type diffusion layer, and the drain having an average n-type dopant concentration of at least 1×10 19 ions/cm 3 ; and a p-type region in junction relation with the source and operating in combination with the source to define a tunnel diode, the p-type region being connected to a third voltage higher than the first voltage.

Claim 12

A static memory cell comprising: a p-type semiconductor substrate having an average p-type dopant concentration of at least 1×10 16 ions/cm 3 and being connected to a first voltage; a buried n-type diffusion layer in the substrate, the n-type layer having an average n-type dopant concentration of at least 1×10 19 ions/cm 3 and being connected to a second voltage lower than the first voltage; an n-channel transistor formed relative to the substrate over the buried n-type layer, the n-channel transistor having a source, a gate, and a drain, the source having an average n-type dopant concentration of at least 1×10 19 ions/cm 3 and the source having a lowermost portion which is ≦0.1 micron above the n-type diffusion layer, and the drain having an average n-type dopant concentration of at least 1×10 19 ions/cm 3 ; and a p-type region in junction relation with the source and operating in combination with the source to define a tunnel diode, the p-type region being connected to a third voltage higher than the first voltage.

Claim 13

A static memory cell comprising: an n-type semiconductor substrate having an average n-type dopant concentration of at least 1×10 16 ions/cm 3 and being connected to a first voltage; a buried p-type diffusion layer in the substrate, the p-type layer having an average p-type dopant concentration of at least 1×10 19 ions/cm 3 and being connected to a second voltage above the first voltage; a p-channel transistor formed relative to the substrate over the buried p-type layer, the p-channel transistor having a source, a gate, and a drain, the source having an average p-type dopant concentration of at least 1×10 19 ions/cm 3 and the source having a lowermost portion which is ≦0.4 micron above the p-type diffusion layer, and the drain having an average p-type dopant concentration of at least 1×10 19 ions/cm 3 ; and an n-type region in junction relation with the source and operating in combination with the source to define a tunnel diode, the n-type region being connected to a third voltage lower than the first voltage.

Claim 14

A static memory cell comprising: an n-type semiconductor substrate having an average n-type dopant concentration of at least 1×10 16 ions/cm 3 and being connected to a first voltage; a buried p-type diffusion layer in the substrate, the p-type layer having an average p-type dopant concentration of at least 1×10 19 ions/cm 3 and being connected to a second voltage above the first voltage; a p-channel transistor formed relative to the substrate over the buried p-type layer, the p-channel transistor having a source, a gate, and a drain, the source having an average p-type dopant concentration of at least 1×10 19 ions/cm 3 and the source having a lowermost portion which is ≦0.4 micron above the p-type diffusion layer, and the drain having an average p-type dopant concentration of at least 1×10 19 ions/cm 3 ; and an n-type region in junction relation with the source and operating in combination with the source to define a tunnel diode, the n-type region being connected to a third voltage lower than the first voltage.

Claim 15

A static memory cell comprising: an n-type semiconductor substrate having an average n-type dopant concentration of at least 1×10 16 ions/cm 3 and being connected to a first voltage; a buried p-type diffusion layer in the substrate, the p-type layer having an average p-type dopant concentration of at least 1×10 19 ions/cm 3 and being connected to a second voltage above the first voltage; a p-channel transistor formed relative to the substrate over the buried p-type layer, the p-channel transistor having a source, a gate, and a drain, the source having an average p-type dopant concentration of at least 1×10 19 ions/cm 3 and the source having a lowermost portion which is ≦0.1 micron above the p-type diffusion layer, and the drain having an average p-type dopant concentration of at least 1×10 19 ions/cm 3 ; and an n-type region in junction relation with the source and operating in combination with the source to define a tunnel diode, the n-type region being connected to a third voltage lower than the first voltage.

Claim 16

A static memory cell comprising: an n-type semiconductor substrate having an average n-type dopant concentration of at least 1×10 16 ions/cm 3 and being connected to a first voltage; a buried p-type diffusion layer in the substrate, the p-type layer having an average p-type dopant concentration of at least 1×10 19 ions/cm 3 and being connected to a second voltage above the first voltage; a p-channel transistor formed relative to the substrate over the buried p-type layer, the p-channel transistor having a source, a gate, and a drain, the source having an average p-type dopant concentration of at least 1×10 19 ions/cm 3 and the source having a lowermost portion which is ≦0.1 micron above the p-type diffusion layer, and the drain having an average p-type dopant concentration of at least 1×10 19 ions/cm 3 ; and an n-type region in junction relation with the source and operating in combination with the source to define a tunnel diode, the n-type region being connected to a third voltage lower than the first voltage.

Claim 17

A memory device comprising: a static random access memory cell to which information can be written multiple times and from which information can be read multiple times, the memory cell including a p-type semiconductor substrate having an average p-type dopant concentration of at least 1×10 16 ions/cm 3 ; a buried n-type layer in the substrate, the n-type layer having an average n-type dopant concentration of at least 1×10 19 ; an n-channel transistor formed relative to the substrate over the buried n-type layer, the n-channel transistor having a source defining a memory node, a gate, and a drain, the source having an average n-type dopant concentration of at least 1×10 19 ions/cm 3 ; the memory node, the buried layer, and the substrate defining a parasitic transistor with the substrate acting as the base of the parasitic transistor, the memory node acting as the collector of the parasitic transistor, and the buried layer acting as the emitter of the parasitic transmitter; and a p+ region in junction relation with the source and operating in combination with the source to define a tunnel diode, the p-type semiconductor substrate being forward biased relative to the buried n-type layer, and the parasitic transistor being forward biased to act as a current sink for the memory node.

Claim 18

A memory device comprising: a static random access memory cell to which information can be written multiple times and from which information can be read multiple times, the memory cell including a p-type semiconductor substrate having an average p-type dopant concentration of at least 1×10 16 ions/cm 3 ; a buried n-type layer in the substrate, the n-type layer having an average n-type dopant concentration of at least 1×10 19 ; an n-channel transistor formed relative to the substrate over the buried n-type layer, the n-channel transistor having a source defining a memory node, a gate, and a drain, the source having an average n-type dopant concentration of at least 1×10 19 ions/cm 3 ; the memory node, the buried layer, and the substrate defining a parasitic transistor with the substrate acting as the base of the parasitic transistor, the memory node acting as the collector of the parasitic transistor, and the buried layer acting as the emitter of the parasitic transmitter; and a p+ region in junction relation with the source and operating in combination with the source to define a tunnel diode, the p-type semiconductor substrate being forward biased relative to the buried n-type layer, and the parasitic transistor being forward biased to act as a current sink for the memory node.

Claim 19

A memory device comprising: a static random access memory cell to which information can be written multiple times and from which information can be read multiple times, the memory cell including an n-type semiconductor substrate having an average n-type dopant concentration of at least 1×10 16 ions/cm 3 ; a buried p-type layer in the substrate, the p-type layer having an average p-type dopant concentration of at least 1×10 19 ; a p-channel transistor formed relative to the substrate over the buried p-type layer, the p-channel transistor having a source defining a memory node, a gate, and a drain, the source having an average p-type dopant concentration of at least 1×10 19 ions/cm 3 ; the memory node, the buried layer, and the substrate defining a parasitic transistor with the substrate acting as the base of the parasitic transistor, the memory node acting as the collector of the parasitic transistor, and the buried layer acting as the emitter of the parasitic transistor; and an n+ region in junction relation with the source and operating in combination with the source to define a tunnel diode, the n-type semiconductor substrate being connected to a first voltage, the buried p-type layer being connected to a second voltage above the first voltage, the n+ region being connected to a third voltage lower than the first voltage, and the parasitic transistor being forward biased to act as a current sink for the memory node.

Claim 20

A memory device comprising: a static random access memory cell to which information can be written multiple times and from which information can be read multiple times, the memory cell including an n-type semiconductor substrate having an average n-type dopant concentration of at least 1×10 16 ions/cm 3 ; a buried p-type layer in the substrate, the p-type layer having an average p-type dopant concentration of at least 1×10 19 ; a p-channel transistor formed relative to the substrate over the buried p-type layer, the p-channel transistor having a source defining a memory node, a gate, and a drain, the source having an average p-type dopant concentration of at least 1×10 19 ions/cm 3 ; the memory node, the buried layer, and the substrate defining a parasitic transistor with the substrate acting as the base of the parasitic transistor, the memory node acting as the collector of the parasitic transistor, and the buried layer acting as the emitter of the parasitic transistor; and an n+ region in junction relation with the source and operating in combination with the source to define a tunnel diode, the n-type semiconductor substrate being connected to a first voltage, the buried p-type layer being connected to a second voltage above the first voltage, the n+ region being connected to a third voltage lower than the first voltage, and the parasitic transistor being forward biased to act as a current sink for the memory node.