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US5625797A
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Automatic optimization of a compiled memory structure based on user selected criteria
Assignee: NXP BV
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Filing: 1993-11-03
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Granted: 1997-04-29
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Expires: 2013-11-03
Abstract
Abstract A block compiler system that allows a user to specify the total number of words and bits per word in a memory structure and to choose among alternative memory structures according to a user-selected criterion. In operation, the system varies the partitioning of memory address lines among column address lines and row address lines. Further, the system varies the internal memory structure according to a selected partitioning of memory address lines among column address lines and row address lines, and optimizes the memory structure based upon higher-level user-selected criteria.
Inventors
- 👤 Thomas V. Ferry
- 👤 Russell L. Steinweg
- 👤 Michael A. Zampaglione
- 👤 Pei H. Lin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 14:26
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1006
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
168 words
A compiler system for allowing a user to specify the total number of words and bits per word in a memory structure and to choose among alternative structures for the specified memory structure according to a selected criterion, comprising: means for selectively varying the partitioning of memory address lines in a memory structure among column address lines and row address lines; means for selectively varying a memory structure in terms of the number of rows and columns according to the selected partitioning of memory address lines among column address lines and row address lines; and means for optimizing the memory structure during compilation thereof by automatically selecting an optimal structure based upon at least one higher-level user-selectable criterion which defines a user-specified constraint of the compiled memory structure, wherein the at least one higher-level user-selectable criterion includes at least one of a selected area, a total number of gate sites occupied by the memory structure, an aspect ratio, and a minimum access time of the overall compiled memory.
Claim 2
Dependent Claim
168 words
A compiler system for allowing a user to specify the total number of words and bits per word in a memory structure and to choose among alternative structures for the specified memory structure according to a selected criterion, comprising: means for selectively varying the partitioning of memory address lines in a memory structure among column address lines and row address lines; means for selectively varying a memory structure in terms of the number of rows and columns according to the selected partitioning of memory address lines among column address lines and row address lines; and means for optimizing the memory structure during compilation thereof by automatically selecting an optimal structure based upon at least one higher-level user-selectable criterion which defines a user-specified constraint of the compiled memory structure, wherein the at least one higher-level user-selectable criterion includes at least one of a selected area, a total number of gate sites occupied by the memory structure, an aspect ratio, and a minimum access time of the overall compiled memory.
Claim 3
Dependent Claim
17 words
A system according to claim 1 wherein elements in the memory structure are random access memory elements.
Claim 4
Dependent Claim
16 words
A system according to claim 1 wherein the compiler system is a gate array block compiler.
Claim 5
Dependent Claim
154 words
A process for implementing a block compiler system such that the system allows a user to specify the total number of words in a memory structure and to choose among alternative structures for the specified memory structure according to a selected criterion, comprising: selecting the total number of words in a memory structure of an application-specific integrated circuit; selectively varying the partitioning of memory address lines of the memory structure, in terms of column address lines and row address lines; and optimizing the memory structure by selecting an optimal structure based on at least one higher-level user-selected criterion during compilation of the memory structure which defines a user-specified constraint of the compiled memory structure, wherein the at least one higher-level user-selectable criterion includes at least one of a selected area, a total number of gate sites occupied by the memory, an aspect ratio, and a minimum access time of the overall compiled memory structure.
Claim 6
Dependent Claim
154 words
A process for implementing a block compiler system such that the system allows a user to specify the total number of words in a memory structure and to choose among alternative structures for the specified memory structure according to a selected criterion, comprising: selecting the total number of words in a memory structure of an application-specific integrated circuit; selectively varying the partitioning of memory address lines of the memory structure, in terms of column address lines and row address lines; and optimizing the memory structure by selecting an optimal structure based on at least one higher-level user-selected criterion during compilation of the memory structure which defines a user-specified constraint of the compiled memory structure, wherein the at least one higher-level user-selectable criterion includes at least one of a selected area, a total number of gate sites occupied by the memory, an aspect ratio, and a minimum access time of the overall compiled memory structure.
Claim 7
Dependent Claim
18 words
A process according to claim 4 wherein the elements in the memory structure are random access memory elements.
Claim 8
Dependent Claim
17 words
A process according to claim 4 wherein the compiler system is a gate array block compiler system.
Claim 9
Dependent Claim
27 words
A process according to claim 4 further including a step of selecting a number of bits per word for the memory structure of an application-specific integrated circuit.
References Cited (Backward Citations)
US4035778A
Cited
US4663742A
Cited
US4847755A
Cited
US5021947A
Cited
US4811297A
Cited
US4885684A
Cited
US5093916A
Cited
US5247668A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-04-28 | 2000-10-28 | 2001-04-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-04-28 | 2004-10-28 | 2005-04-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-04-28 | 2008-10-28 | 2009-04-29 | $7700.00 | Window Closed / Lapsed |