Patent US5625779A successfully refreshed from Google Patents.
US5625779A
Expired / Lapsed
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Arbitration signaling mechanism to prevent deadlock guarantee access latency, and guarantee acquisition latency for an expansion bridge
Assignee: Intel Corp
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Filing: 1994-12-30
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Granted: 1997-04-29
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Expires: 2014-12-30
Abstract
Abstract An arbitration signaling mechanism for an intermediate bus coupled between an expansion bridge and a host bridge that manages communication over the intermediate bus. The host bridge includes a CPU posting buffer for posting transactions between a CPU and the expansion bridge, and a DRAM buffer for storing data to be written into the DRAM. The host bridge also includes an arbiter coupled to receive a request signal from the expansion bridge and any other bus agents coupled to the expansion bridge. Responsive to a request from the expansion bridge, the arbiter empties the CPU posting buffer and the DRAM buffer before asserting an acknowledge signal. A passive release method is provided, which includes signaling a passive release semantic by the expansion bridge during a communication cycle in which the expansion bridge has bus control. The host bridge can grant temporary use of the bus to another bus agent before again granting access to the expansion bridge.
Inventors
- 👤 Gary A. Solomon
- 👤 Peter D. MacWilliams
- 👤 George R. Hayek
- 👤 Nicholas D. Wade
- 👤 Abid Asghar
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 06:45
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/36; G06F13/362; G06F13/364; G06F13/38; G06F13/40; G06F13/4004; G06F13/4027; G06F13/4031; G06F13/4036
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
201 words
A passive release method for an expansion bridge and a host bridge coupled to an intermediate bus, said host bridge including an arbiter, a CPU posting buffer, and a DRAM buffer, said passive release method comprising the steps of: said expansion bridge asserting an intermediate bus request to said arbiter; said arbiter arbitrating said intermediate bus request; said expansion bridge winning said arbitration; emptying said CPU posting buffer after said expansion bridge has won arbitration; after emptying said CPU posting buffer, asserting a grant signal to said expansion bridge to allow said expansion bridge use of said intermediate bus for a transaction; said expansion bridge determining whether it can relinquish control of said intermediate bus before said transaction is complete; said expansion bridge signaling a release signal to relinquish control of said intermediate bus before said transaction is complete; said expansion bridge then immediately re-asserting said intermediate bus request to said arbiter; and said arbiter granting control of said expansion bridge to an agent coupled to said intermediate bus if said agent has higher priority than said expansion bridge, otherwise said arbiter returning control of said intermediate bridge to said expansion bridge, allowing said expansion bridge to continue with said transaction.
Claim 2
Dependent Claim
201 words
A passive release method for an expansion bridge and a host bridge coupled to an intermediate bus, said host bridge including an arbiter, a CPU posting buffer, and a DRAM buffer, said passive release method comprising the steps of: said expansion bridge asserting an intermediate bus request to said arbiter; said arbiter arbitrating said intermediate bus request; said expansion bridge winning said arbitration; emptying said CPU posting buffer after said expansion bridge has won arbitration; after emptying said CPU posting buffer, asserting a grant signal to said expansion bridge to allow said expansion bridge use of said intermediate bus for a transaction; said expansion bridge determining whether it can relinquish control of said intermediate bus before said transaction is complete; said expansion bridge signaling a release signal to relinquish control of said intermediate bus before said transaction is complete; said expansion bridge then immediately re-asserting said intermediate bus request to said arbiter; and said arbiter granting control of said expansion bridge to an agent coupled to said intermediate bus if said agent has higher priority than said expansion bridge, otherwise said arbiter returning control of said intermediate bridge to said expansion bridge, allowing said expansion bridge to continue with said transaction.
Claim 3
Dependent Claim
43 words
The passive release method of claim 1, further comprising the step of: emptying said DRAM buffer after said expansion bridge has won arbitration but before asserting said grant signal to said expansion bridge to allow said expansion bridge use of said intermediate bus.
Claim 4
Dependent Claim
54 words
The passive release method of claim 1, further comprising the step of said arbiter maintaining said intermediate bus request by said expansion bridge to use said intermediate bus after said expansion bridge relinquishes control of said intermediate bus, arbitrating other requests, and subsequently granting use of said intermediate bus back to said expansion bridge.
Claim 5
Dependent Claim
50 words
The passive release method of claim 1 wherein said host bridge is coupled to a CPU, and said CPU is prevented from posting data to said CPU posting buffer for a period beginning after the expansion bridge has won arbitration and ending when said expansion bridge has completed said transaction.
Claim 6
Dependent Claim
179 words
An arbitration signaling system, comprising: an expansion bridge; an intermediate bus; a host bridge coupled to said expansion bridge and said intermediate bus, said host bridge including an arbiter, a CPU posting buffer, and a DRAM buffer wherein said arbiter arbitrates requests from said intermediate bus, said CPU posting buffer is emptied after said expansion bridge has won arbitration, and a grant signal is asserted to said expansion bridge to allow said expansion bridge use of said intermediate bus for a transaction; said expansion bridge determining whether it can relinquish control of said intermediate bus before said transaction is complete and signaling a release signal to relinquish control of said intermediate bus before said transaction is complete; said expansion bridge then immediately re-asserting said intermediate bus request to said arbiter; and said arbiter granting control of said expansion bridge to an agent coupled to said intermediate bus if said agent has higher priority than said expansion bridge, otherwise said arbiter returning control of said intermediate bridge to said expansion bridge, allowing said expansion bridge to continue with said transaction.
Claim 7
Dependent Claim
179 words
An arbitration signaling system, comprising: an expansion bridge; an intermediate bus; a host bridge coupled to said expansion bridge and said intermediate bus, said host bridge including an arbiter, a CPU posting buffer, and a DRAM buffer wherein said arbiter arbitrates requests from said intermediate bus, said CPU posting buffer is emptied after said expansion bridge has won arbitration, and a grant signal is asserted to said expansion bridge to allow said expansion bridge use of said intermediate bus for a transaction; said expansion bridge determining whether it can relinquish control of said intermediate bus before said transaction is complete and signaling a release signal to relinquish control of said intermediate bus before said transaction is complete; said expansion bridge then immediately re-asserting said intermediate bus request to said arbiter; and said arbiter granting control of said expansion bridge to an agent coupled to said intermediate bus if said agent has higher priority than said expansion bridge, otherwise said arbiter returning control of said intermediate bridge to said expansion bridge, allowing said expansion bridge to continue with said transaction.
Claim 8
Dependent Claim
41 words
The arbitration signaling system of claim 5 wherein said DRAM buffer is emptied after said expansion bridge has won arbitration but before said grant signal is asserted to said expansion bridge to allow said expansion bridge use of said intermediate bus.
Claim 9
Dependent Claim
51 words
The arbitration signaling system of claim 5 wherein said arbiter further maintains said intermediate bus request by said expansion bridge to use said intermediate bus after said expansion bridge relinquishes control of said intermediate bus, arbitrates other requests, and subsequently grants use of said intermediate bus back to said expansion bridge.
Claim 10
Dependent Claim
50 words
The arbitration signaling system of claim 5 wherein said host bridge is coupled to a CPU, and said CPU is prevented from posting data to said CPU posting buffer for a period beginning after the expansion bridge has won arbitration and ending when said expansion bridge has completed said transaction.
References Cited (Backward Citations)
US5257356A
Cited
US5265211A
Cited
US5416910A
Cited
US5467295A
Cited
US5392407A
Cited
US5469435A
Cited
US5519838A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-04-28 | 2000-10-28 | 2001-04-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-04-28 | 2004-10-28 | 2005-04-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-04-28 | 2008-10-28 | 2009-04-29 | $7700.00 | Window Closed / Lapsed |