US5623610A
Expired / Lapsed
US
⏱️ 0.0 years remaining
System for assigning geographical addresses in a hierarchical serial bus by enabling upstream port and selectively enabling disabled ports at power on/reset
Assignee: Intel Corp
•
Filing: 1994-10-31
•
Granted: 1997-04-22
•
Expires: 2014-10-31
Abstract
Abstract Circuitry and complementary logic are provided to a bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces of an hierarchical serial bus assembly for the bus controller to dynamically detect and manage the interconnection topology of the serial bus elements. The serial bus assembly is used to serially interface a number of isochronous and asynchronous peripherals to the system unit of a computer system. These circuitry and complementary logic support an hierarchical view of the serial bus elements, logically dividing the hierarchy into multiple tiers. This logical view of the serial bus elements is used by the bus controller to detect the presence of interconnected serial bus elements and the functions of the bus agents, i.e. the system unit and the interconnected peripheral, as well as assignment of addresses to the serial bus elements and the functions, at power on, reset, and during operation when serial bus elements are hot attached to or detached from the serial bus assembly.
Inventors
- 👤 Shaun Knoll
- 👤 Jeff C. Morriss
- 👤 Shelagh Callahan
- 👤 Ajay V. Bhatt
- 👤 Sudarshan B. Cadambi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 20:37
CPC Classifications
H; H04; H04L; H04L12/00; H04L12/28; H04L12/40; H04L12/40052; H04L12/40058; G; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0646; G06F12/0653; G06F12/0661; G06F12/0684; G06F13/00; G06F13/38; G06F13/382; G06F13/385; H04L12/40078
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
263 words
An apparatus for dynamically determining and managing connection topology of a serial bus assembly including a bus controller, one or more bus signal distributors, and one or more bus interfaces for hierarchically interconnecting one or more peripherals to a system unit of a computer system, each bus interface being coupled to a bus signal distributor, which in turn is coupled to another bus signal distributor, except for one bus signal distributor, which is coupled to the bus controller, said apparatus comprising: first circuitry for initializing each bus signal distributor and each bus interface with a predetermined default common geographical address at power on/reset, and for subsequently replacing the common geographical address with a unique geographical address assigned by the bus controller that is reflective of the one or more bus signal distributors and the one or more bus interfaces' topological positions in the serial bus assembly; second circuitry for enabling an upstream port and disabling all other ports of each bus signal distributor at power on/reset, and for selectively enabling the disabled ports as instructed by the bus controller; and third circuitry and complementary logic, coupled to the first and second circuitry, for facilitating the bus controller to employ a logical hierarchical view of the serial bus assembly to selectively instructing the disabled ports of the bus signal distributors to be enabled, one disabled port at a time, to incrementally detect the presence of each bus signal distributor/bus interface, and assign a unique geographical address to each detected bus signal distributor/bus interface, in a systematic manner, at power on/reset and periodically during operation.
Claim 2
Independent Claim
263 words
An apparatus for dynamically determining and managing connection topology of a serial bus assembly including a bus controller, one or more bus signal distributors, and one or more bus interfaces for hierarchically interconnecting one or more peripherals to a system unit of a computer system, each bus interface being coupled to a bus signal distributor, which in turn is coupled to another bus signal distributor, except for one bus signal distributor, which is coupled to the bus controller, said apparatus comprising: first circuitry for initializing each bus signal distributor and each bus interface with a predetermined default common geographical address at power on/reset, and for subsequently replacing the common geographical address with a unique geographical address assigned by the bus controller that is reflective of the one or more bus signal distributors and the one or more bus interfaces' topological positions in the serial bus assembly; second circuitry for enabling an upstream port and disabling all other ports of each bus signal distributor at power on/reset, and for selectively enabling the disabled ports as instructed by the bus controller; and third circuitry and complementary logic, coupled to the first and second circuitry, for facilitating the bus controller to employ a logical hierarchical view of the serial bus assembly to selectively instructing the disabled ports of the bus signal distributors to be enabled, one disabled port at a time, to incrementally detect the presence of each bus signal distributor/bus interface, and assign a unique geographical address to each detected bus signal distributor/bus interface, in a systematic manner, at power on/reset and periodically during operation.
Claim 3
Dependent Claim
85 words
The apparatus as set forth in claim 1, wherein said first circuitry comprises a plurality of initialization circuitry correspondingly disposed on said one or more bus signal distributors and said one or more bus interfaces, one initialization circuitry for each bus signal distributor/bus interface, for initializing each of said one or more bus signal distributors and one or more bus interfaces to the predetermined default common geographical address at power on/reset, and for subsequently replacing the common geographical address with the assigned unique geographical address.
Claim 4
Dependent Claim
90 words
The apparatus as set forth in claim 1, wherein said second circuitry comprises a plurality of port enabling/disabling circuitry correspondingly disposed on said one or more bus signal distributors, one port enabling/disabling circuitry for each bus signal distributor, for selectively enabling and disabling ports of each of said one or more bus signal distributors, including enabling the upstream port and disabling all other ports of each of said one or more bus signal distributors at power on/reset as well as enabling/disabling a disabled/enabled port as instructed by the bus controller.
Claim 5
Dependent Claim
85 words
The apparatus as set forth in claim 3, wherein, said third circuitry and complementary logic comprises first control circuitry and complementary logic disposed on said bus controller for assigning a unique geographical address to a bus interface, whenever the bus interface is detected, said first control circuitry and complementary logic further determining how many functions are supported by a peripheral hosting the bus interface, and assigning a unique logical address to each of the functions, upon assigning a unique geographical address to the bus interface.
Claim 6
Dependent Claim
83 words
The apparatus as set forth in claim 4, wherein, said third circuitry and complementary logic further comprises second control circuitry and complementary logic disposed on said bus controller for systematically instructing the disabled ports of a bus signal distributor to be enabled, one port at a time, detecting if a bus interface is connected to a port once the port is enabled, and instructing the port to be disabled again if no bus interface is detected, whenever the bus signal distributor is detected.
Claim 7
Dependent Claim
235 words
In a computer system comprising a serial bus assembly, including a bus controller, one or more bus signal distributors, and one or more bus interfaces, for hierarchically interconnecting one or more peripherals to a system unit of the computer system, each bus interface being coupled upstream to a bus signal distributor, which in turn is coupled upstream to another bus signal distributor, with the exception of one bus signal distributor, which is coupled upstream to the bus controller, a method for dynamically determining and managing connection topology of the serial bus assembly, the method comprising the steps of: a) initializing each bus signal distributor and each bus interface with a predetermined default common geographical address at power on/reset; b) enabling an upstream port and disabling all other ports of each bus signal distributor at power on/reset; and c) selectively instructing the disabled ports to be enabled, one at a time, to incrementally detecting the presence of each bus signal distributor/bus interface, employing a logical hierarchical view of the serial bus assembly, and assigning a unique geographical address to each detected bus signal distributor/bus interface to replace the predetermined default common geographical address, in a systematic manner, at power on/reset, and periodically during operation, by the bus controller, the unique geographical address being reflective of the one or more bus signal distributors and the one or more bus interface's topological positions in the serial bus assembly.
Claim 8
Dependent Claim
235 words
In a computer system comprising a serial bus assembly, including a bus controller, one or more bus signal distributors, and one or more bus interfaces, for hierarchically interconnecting one or more peripherals to a system unit of the computer system, each bus interface being coupled upstream to a bus signal distributor, which in turn is coupled upstream to another bus signal distributor, with the exception of one bus signal distributor, which is coupled upstream to the bus controller, a method for dynamically determining and managing connection topology of the serial bus assembly, the method comprising the steps of: a) initializing each bus signal distributor and each bus interface with a predetermined default common geographical address at power on/reset; b) enabling an upstream port and disabling all other ports of each bus signal distributor at power on/reset; and c) selectively instructing the disabled ports to be enabled, one at a time, to incrementally detecting the presence of each bus signal distributor/bus interface, employing a logical hierarchical view of the serial bus assembly, and assigning a unique geographical address to each detected bus signal distributor/bus interface to replace the predetermined default common geographical address, in a systematic manner, at power on/reset, and periodically during operation, by the bus controller, the unique geographical address being reflective of the one or more bus signal distributors and the one or more bus interface's topological positions in the serial bus assembly.
Claim 9
Dependent Claim
38 words
The method as set forth in claim 6, wherein step (a) comprises self-initializing each of said one or more bus signal distributors and one or more bus interfaces to the predetermined default common geographical address at power on/reset.
Claim 10
Dependent Claim
74 words
The method as set forth in claim 7, wherein, step (c) further comprises assigning by the bus controller a unique geographical address to a bus interface upon detecting the bus interface, and determining by the bus controller how many functions are supported by a peripheral hosting the detected bus interface, and assigning by the bus controller a logical address to each of the functions, upon assigning a unique geographical address to the bus interface.
Claim 11
Dependent Claim
71 words
The method as set forth in claim 8, wherein, step (c) comprises systematically instructing the disabled ports of a bus signal distributor to be enable, by the bus controller, one port at a time, detecting if a bus interface is connected to a port by the bus controller once the port is enabled, and instructing the port to be disabled again by the bus controller if no bus interface is detected.
Claim 12
Dependent Claim
218 words
A computer system bus controller for interconnecting one or more peripherals to a system unit through one or more bus interfaces and one or more bus signals distributors, each bus interface being coupled upstream to a bus signal distributor, which in turn is coupled upstream to another bus signal distributor, with the exception of one bus signal distributor, which is coupled upstream to the bus controller, the bus controller comprising circuitry and complementary logic for selectively instructing disabled ports of the bus signal distributors to be enabled, one at a time, to incrementally detect the presence of the one or more bus signal distributors, and the presence of the one or more bus interfaces, and assigning a unique geographical address to each detected bus signal distributor/bus interface to replace a predetermined default common geographical address, at power on/reset and periodically during operation, in a systematic manner, employing a logical hierarchical view, the unique geographical address being reflective of the one or more bus signal distributors and the one or more bus interfaces' topological positions in the serial bus assembly; each of the bus signal distributors/bus interfaces is initialized to the predetermined default common geographical address at power on/reset, whereas each of the bus signal distributors enabling only an upstream port and disabling all other ports at power on/reset.
Claim 13
Dependent Claim
218 words
A computer system bus controller for interconnecting one or more peripherals to a system unit through one or more bus interfaces and one or more bus signals distributors, each bus interface being coupled upstream to a bus signal distributor, which in turn is coupled upstream to another bus signal distributor, with the exception of one bus signal distributor, which is coupled upstream to the bus controller, the bus controller comprising circuitry and complementary logic for selectively instructing disabled ports of the bus signal distributors to be enabled, one at a time, to incrementally detect the presence of the one or more bus signal distributors, and the presence of the one or more bus interfaces, and assigning a unique geographical address to each detected bus signal distributor/bus interface to replace a predetermined default common geographical address, at power on/reset and periodically during operation, in a systematic manner, employing a logical hierarchical view, the unique geographical address being reflective of the one or more bus signal distributors and the one or more bus interfaces' topological positions in the serial bus assembly; each of the bus signal distributors/bus interfaces is initialized to the predetermined default common geographical address at power on/reset, whereas each of the bus signal distributors enabling only an upstream port and disabling all other ports at power on/reset.
Claim 14
Dependent Claim
73 words
The computer system bus controller as set forth in claim 10, wherein said circuitry and complementary logic comprises first control circuitry and complementary logic for assigning a unique geographical address to a bus interface, upon detecting the bus interface, determining how many functions are supported by a peripheral hosting the bus interface, and assigning a unique logical address to each of the functions, upon assigning a unique geographical address to the bus interface.
Claim 15
Dependent Claim
80 words
The computer system bus controller as set forth in claim 11, wherein, said circuitry and complementary logic further comprises second control circuitry and complementary logic for systematically instructing the disabled ports of a bus signal distributor to be enabled, one port at a time, detecting if a bus interface is connected to a port once the port is enabled, and instructing the port to be disabled again if no bus interface is detected, whenever the bus signal distributor is detected.
Claim 16
Dependent Claim
162 words
A computer system bus signal distributor comprising: a plurality of ports including a first port, the first port being used to couple the bus signal distributor upstream to either another bus signal distributor or the bus controller, and the remaining ports being used to couple lower level bus interfaces or other lower level bus signal distributors upstream to the bus signal distributor; first circuitry for initializing the bus signal distributor with a predetermined default common geographical address at power on/reset, and for subsequently replacing the common geogaphical address with a unique geographical address assigned by the bus controller; the unique geographical address being reflective of the bus signal distributor's topological position in the serial bus assembly; and second circuitry coupled to the ports and to the first circuitry for automatically enabling the first port and disabling all other ports at power on/reset, and for selectively enabling the other ports responsive to commands addressed to the bus signal distributor by the bus controller.
Claim 17
Dependent Claim
162 words
A computer system bus signal distributor comprising: a plurality of ports including a first port, the first port being used to couple the bus signal distributor upstream to either another bus signal distributor or the bus controller, and the remaining ports being used to couple lower level bus interfaces or other lower level bus signal distributors upstream to the bus signal distributor; first circuitry for initializing the bus signal distributor with a predetermined default common geographical address at power on/reset, and for subsequently replacing the common geogaphical address with a unique geographical address assigned by the bus controller; the unique geographical address being reflective of the bus signal distributor's topological position in the serial bus assembly; and second circuitry coupled to the ports and to the first circuitry for automatically enabling the first port and disabling all other ports at power on/reset, and for selectively enabling the other ports responsive to commands addressed to the bus signal distributor by the bus controller.
Claim 18
Dependent Claim
184 words
A bus interface for coupling a peripheral to a system unit through zero or more bus signal distributors and a bus controller, the bus interface comprising: first circuitry for self-initializing the bus interface with a predetermined default common geographical address at power on/reset, and for subsequently replacing the common geographical address with a unique geographical address assigned by the bus controller, the unique geographical address being reflective of the bus interface's topological position in the serial bus assembly; second circuitry coupled to the first circuitry and to the bus controller through the zero or more bus signal distributors for accepting an geographical address assignment by the bus controller, each of the bus signal distributor enabling an upstream port and disabling all other ports at power on/reset, and then enabling the disabled ports, one at a time, at the instruction of the bus controller; and third circuitry coupled to the second circuitry and to the bus controller through the zero or more bus signal distributors for facilitating at least one logical address assignment by the bus controller to at least one function of the peripheral.
Claim 19
Dependent Claim
184 words
A bus interface for coupling a peripheral to a system unit through zero or more bus signal distributors and a bus controller, the bus interface comprising: first circuitry for self-initializing the bus interface with a predetermined default common geographical address at power on/reset, and for subsequently replacing the common geographical address with a unique geographical address assigned by the bus controller, the unique geographical address being reflective of the bus interface's topological position in the serial bus assembly; second circuitry coupled to the first circuitry and to the bus controller through the zero or more bus signal distributors for accepting an geographical address assignment by the bus controller, each of the bus signal distributor enabling an upstream port and disabling all other ports at power on/reset, and then enabling the disabled ports, one at a time, at the instruction of the bus controller; and third circuitry coupled to the second circuitry and to the bus controller through the zero or more bus signal distributors for facilitating at least one logical address assignment by the bus controller to at least one function of the peripheral.
References Cited (Backward Citations)
US3245045A
Cited
US3916387A
Cited
US3932841A
Cited
US4070704A
Cited
US4092491A
Cited
US4409656A
Cited
US4689740A
Cited
US4713834A
Cited
US4660141A
Cited
US4748346A
Cited
US4870704A
Cited
US4606052A
Cited
US4984190A
Cited
US4885742A
Cited
US4912633A
Cited
US4914650A
Cited
US5317597A
Cited
US5257160A
Cited
US5001707A
Cited
US5179670A
Cited
US5063574A
Cited
US5130983A
Cited
US5237690A
Cited
US5269011A
Cited
US5173939A
Cited
US5282202A
Cited
US5341131A
Cited
US5386567A
Cited
US5341480A
Cited
US5379384A
Cited
US5483518A
Cited
US5463620A
Cited
US5361261A
Cited
US5440556A
Cited
US5446765A
Cited
US5394556A
Cited
US5542055A
Cited
US5418478A
Cited
US5440181A
Cited
US5463624A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-04-21 | 2000-10-21 | 2001-04-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-04-21 | 2004-10-21 | 2005-04-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-04-21 | 2008-10-21 | 2009-04-22 | $7700.00 | Window Closed / Lapsed |