Patent JPS5583383A successfully refreshed from Google Patents.
Patent US5622899A successfully refreshed from Google Patents.
US5622899A
Expired / Lapsed
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Method of fabricating semiconductor chips separated by scribe lines used for endpoint detection
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1996-04-22
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Granted: 1997-04-22
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Expires: 2016-04-22
Abstract
Abstract A process has been developed in which photoresist thinning at the edges of silicon chips, resulting from photoresist flowing from semiconductor chips, exhibiting features with raised topographies, to flat scribe regions, has been reduced. The reduction in photoresist flowing has been accomplished by creating a chessboard pattern of raised insulator and metal features, in the scribe line region, thus reducing the differences in topography between the scribe line and chip regions. The areas between the raised mesas, in the scribe line regions, are used for laser or optical endpoint detection of RIE processes.
Inventors
- 👤 Ying-Chem Chao
- 👤 Chin-Heng Shen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 14:12
CPC Classifications
H; H10; H10P; H10P95/00; H10P95/11; G; G03; G03F; G03F7/00; G03F7/16; H10P76/00; H10P76/20; Y; Y10; Y10S; Y10S438/00; Y10S438/941
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
304 words
A method of fabricating a plurality of regions, containing semiconductor devices, on a semiconductor substrate, using scribe line regions between said regions, comprising the steps of: providing transfer gate transistors on said regions, containing said semiconductor devices; deposition of a first insulator layer on said regions, containing said semiconductor devices, and on said scribe line regions; patterning said first insulator layer to open a contact hole in said first insulator layer, to an element in said regions containing semiconductor devices, and to form first insulator mesas, in a first area of said scribe line regions; deposition of a first metallization layer on said regions and in said contact hole, containing said semiconductor devices, and on said scribe line regions; patterning said first metallization layer to form a first level metal structure on said regions and in said contact hole, containing said semiconductor devices, and to form first metal mesas, in a second area of said scribe line regions; deposition of a second insulator layer on said regions and on said first level metal structure, containing said semiconductor devices, and on said scribe regions including said first insulator mesas; patterning said second insulator layer to open a via hole in said second insulator layer, to expose top surface of said first level metal structure, in said regions, containing said semiconductor devices, and to form second insulator mesas, overlying said first insulator mesas, in said first area of said scribe line regions; deposition of a second metallization layer on said regions, containing said semiconductor devices, and on said scribe line regions; and patterning said second metallization layer to form a second level metal structure on said regions and in said via hole, containing said semiconductor devices, and to form second metal mesas, overlying said first metal mesas, in said second area of said scribe line regions.
Claim 2
Independent Claim
304 words
A method of fabricating a plurality of regions, containing semiconductor devices, on a semiconductor substrate, using scribe line regions between said regions, comprising the steps of: providing transfer gate transistors on said regions, containing said semiconductor devices; deposition of a first insulator layer on said regions, containing said semiconductor devices, and on said scribe line regions; patterning said first insulator layer to open a contact hole in said first insulator layer, to an element in said regions containing semiconductor devices, and to form first insulator mesas, in a first area of said scribe line regions; deposition of a first metallization layer on said regions and in said contact hole, containing said semiconductor devices, and on said scribe line regions; patterning said first metallization layer to form a first level metal structure on said regions and in said contact hole, containing said semiconductor devices, and to form first metal mesas, in a second area of said scribe line regions; deposition of a second insulator layer on said regions and on said first level metal structure, containing said semiconductor devices, and on said scribe regions including said first insulator mesas; patterning said second insulator layer to open a via hole in said second insulator layer, to expose top surface of said first level metal structure, in said regions, containing said semiconductor devices, and to form second insulator mesas, overlying said first insulator mesas, in said first area of said scribe line regions; deposition of a second metallization layer on said regions, containing said semiconductor devices, and on said scribe line regions; and patterning said second metallization layer to form a second level metal structure on said regions and in said via hole, containing said semiconductor devices, and to form second metal mesas, overlying said first metal mesas, in said second area of said scribe line regions.
Claim 3
Dependent Claim
44 words
The method of claim 1, wherein said first insulator layer is a boro-phosphosilicate layer, deposited using LPCVD or PECVD processing, at a temperature between about 350° to 500° C., to a thickness between about 5000 to 15000 Angstroms, using tetraethylorthosilicate, (TEOS), phosphine and diborane.
Claim 4
Dependent Claim
71 words
The method of claim 1, wherein said patterning, used to open said contact hole in said first insulator layer, on said regions, containing said semiconductor devices, and also used to create said first insulator mesas, in said first area of said scribe line regions, is performed via RIE processing, using CHF 3 as an etchant, and using said first area of said scribe line regions, for laser endpoint detection of insulators.
Claim 5
Dependent Claim
40 words
The method of claim 1, wherein said first metallization layer is aluminum, containing between about 1 to 3% copper, and between 0 to 2% silicon, is deposited using r.f. sputtering procedures, to a thickness between about 4000 to 9000 Angstroms.
Claim 6
Dependent Claim
70 words
The method of claim 1, wherein said patterning, used to form said first level metal structure, on said regions, containing said semiconductor devices, and also used to create said first metal mesas, in said second area of said scribe line regions, is performed via RIE processing, using Cl 2 as an etchant, and using said second area, of said scribe line regions, for laser or optical endpoint detection of metals.
Claim 7
Dependent Claim
35 words
The method of claim 1, wherein said second insulator layer is silicon oxide, deposited using PECVD processing, at a temperature between about 300° to 500° C., to a thickness between about 2000 to 5000 Angstroms.
Claim 8
Dependent Claim
78 words
The method of claim 1, wherein said patterning, used to open said via hole in said second insulator layer, on said regions, containing said semiconductor devices, and also used to create said second insulator mesas, overlying said first insulator mesas, in said first area of said scribe line regions, is performed via RIE processing, using CHF 3 as an etchant, and using said first area, of said scribe line regions, for laser or optical endpoint detection of insulators.
Claim 9
Dependent Claim
33 words
The method of claim 1, wherein said second metallization layer is aluminum, containing between about 1 to 3% copper, deposited using r.f. sputtering procedures, to a thickness between about 4000 to 9000 Angstroms.
Claim 10
Dependent Claim
75 words
The method of claim 1, wherein said patterning, used to create said second level metal structure, on said regions, containing said semiconductor devices, and also used to create said second metal mesas, overlying said first metal mesas, in said second area, of said scribe line regions, is performed via RIE processing, using Cl 2 as an etchant, and using said second area, of said scribe line regions, for laser or optical endpoint detection of metals.
Claim 11
Independent Claim
381 words
A method of fabricating semiconductor chips and scribe lines, between said semiconductor chips, on a semiconductor substrate, with scribe line regions comprised of a chessboard pattern of flat regions, used for insulator and metal, RIE endpoint detection sites, and raised insulator and metal mesas, used to provide a topography for said scribe line regions, equivalent to the topography of said semiconductor chips, comprising the steps of: providing transfer gate transistors on said semiconductor chips; deposition of a first insulator layer on said semiconductor chips, and on said scribe line regions; patterning said first insulator layer, using RIE processing, to open a contact hole in said first insulator layer, to an element in said semiconductor chips, and to form first insulator mesas, in an area of said scribe line regions, used for laser or optical endpoint detection of said first insulator layer RIE process; deposition of a first metallization layer on said semiconductor chips and in said contact hole, and on said scribe line regions; patterning said first metallization layer, using RIE processing, to form a first level metal structure on said semiconductor chips and in said contact hole, and to form first metal mesas, in an area of said scribe line regions, used for laser endpoint detection of said first metallization layer RIE process; deposition of a second insulator layer on said semiconductor chips and on said first level metal structure, and on said scribe regions including said first insulator mesas; patterning said second insulator layer, using RIE processing, to open a via hole in said second insulator layer, to expose top surface of said first level metal structure, on said semiconductor chips, and to form second insulator mesas, overlying said first insulator mesas, in said area of said scribe line regions, used for laser endpoint detection of said second insulator RIE process; deposition of a second metallization layer on said semiconductor chips and in said via hole, and on said scribe line regions; and patterning said second metallization layer, using RIE processing, to form a second level metal structure on said semiconductor chips and in said via hole, and to form second metal mesas, overlying said first metal mesas, in said area of said scribe line regions, used for laser or optical endpoint detection of said second metallization RIE process.
Claim 12
Independent Claim
381 words
A method of fabricating semiconductor chips and scribe lines, between said semiconductor chips, on a semiconductor substrate, with scribe line regions comprised of a chessboard pattern of flat regions, used for insulator and metal, RIE endpoint detection sites, and raised insulator and metal mesas, used to provide a topography for said scribe line regions, equivalent to the topography of said semiconductor chips, comprising the steps of: providing transfer gate transistors on said semiconductor chips; deposition of a first insulator layer on said semiconductor chips, and on said scribe line regions; patterning said first insulator layer, using RIE processing, to open a contact hole in said first insulator layer, to an element in said semiconductor chips, and to form first insulator mesas, in an area of said scribe line regions, used for laser or optical endpoint detection of said first insulator layer RIE process; deposition of a first metallization layer on said semiconductor chips and in said contact hole, and on said scribe line regions; patterning said first metallization layer, using RIE processing, to form a first level metal structure on said semiconductor chips and in said contact hole, and to form first metal mesas, in an area of said scribe line regions, used for laser endpoint detection of said first metallization layer RIE process; deposition of a second insulator layer on said semiconductor chips and on said first level metal structure, and on said scribe regions including said first insulator mesas; patterning said second insulator layer, using RIE processing, to open a via hole in said second insulator layer, to expose top surface of said first level metal structure, on said semiconductor chips, and to form second insulator mesas, overlying said first insulator mesas, in said area of said scribe line regions, used for laser endpoint detection of said second insulator RIE process; deposition of a second metallization layer on said semiconductor chips and in said via hole, and on said scribe line regions; and patterning said second metallization layer, using RIE processing, to form a second level metal structure on said semiconductor chips and in said via hole, and to form second metal mesas, overlying said first metal mesas, in said area of said scribe line regions, used for laser or optical endpoint detection of said second metallization RIE process.
Claim 13
Dependent Claim
44 words
The method of claim 10, wherein said first insulator layer is a boro-phoshosilicate layer, deposited using LPCVD or PECVD processing, at a temperature between about 350° to 500° C., to a thickness between about 5000 to 15000 Angstroms, using tetraethylorthosilicate, (TEOS), diborane and phosphine.
Claim 14
Dependent Claim
60 words
The method of claim 10, wherein said patterning, used to open said contact hole in said first insulator layer, on said semiconductor chips, and also used to create said first insulator mesas, in said area of said scribe line regions, used for laser endpoint detection of said first insulator layer RIE process, is performed using CHF 3 as an etchant.
Claim 15
Dependent Claim
40 words
The method of claim 10, wherein said first metallization layer is aluminum, containing between about 1 to 3% copper, and between about 0 to 2% silicon, deposited using r.f. sputtering procedures, to a thickness between about 4000 to 9000 Angstroms.
Claim 16
Dependent Claim
57 words
The method of claim 10, wherein said patterning, used to form said first level metal structure, on said semiconductor chips, and also used to create said first metal mesas, in said area of said scribe line regions, used for laser endpoint detection of said first metallization layer RIE process, is performed using Cl 2 as an etchant.
Claim 17
Dependent Claim
35 words
The method of claim 10, wherein said second insulator layer is silicon oxide, deposited using PECVD processing, at a temperature between about 300° to 500° C., to a thickness between about 2000 to 5000 Angstroms.
Claim 18
Dependent Claim
67 words
The method of claim 10, wherein said patterning, used to open said via hole in said second insulator layer, on said semiconductor chips, and also used to create said second insulator mesas, overlying said first insulator mesas, in said area of said scribe line regions, used for laser or optical endpoint detection of said second insulator layer RIE process, is performed using CHF 3 as an etchant.
Claim 19
Dependent Claim
34 words
The method of claim 10, wherein said second metallization layer is aluminum, containing between about 1 to 3% copper, is deposited using r.f. sputtering procedures, to a thickness between about 4000 to 9000 Angstroms.
Claim 20
Dependent Claim
64 words
The method of claim 10, wherein said patterning, used to create said second level metal structure, on said semiconductor chips, and also used to create said second metal mesas, overlying said first metal mesas, in said area of said scribe line regions, used for laser or optical endpoint detection of said second metallization layer RIE process, is performed using Cl 2 as an etchant.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-04-21 | 2000-10-21 | 2001-04-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-04-21 | 2004-10-21 | 2005-04-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-04-21 | 2008-10-21 | 2009-04-22 | $7700.00 | Window Closed / Lapsed |