US5132252A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for fabricating semiconductor devices that prevents pattern contamination
Assignee: Kyushu Fujitsu Electronics Ltd
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Filing: 1989-04-25
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Granted: 1992-07-21
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Expires: 2009-04-25
Abstract
Abstract A method for preventing contamination caused by residues of etched off patterns etched by photolithographic etching. A considerable amount of small contamination spots on a semiconductor chip are found to be caused by tiny residues of etched off patterns. These residues are formed primarily around the periphery of device areas and mark patterns when their outsides are etched off. The occurence of such residues of etching is increased by anisotropic etching. These residues are dislodged by succeeding steps of the pattern making process, and disperse over the substrate causing small contamination spots. To avoid the detrimental effects of the etching residues, the edges of the mark patterns and device areas are covered with an edge cover which is formed in a step to following the pattern etching process.
Inventors
- 👤 Hidehiko Shiraiwa
- 👤 Hisatsugu Shirai
- 👤 Nobuhiro Takahashi
- 👤 Shinichi Nomura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 08:09
CPC Classifications
H; H10; H10W; H10W46/00; H10W46/501; H10W46/503; Y; Y10; Y10S; Y10S148/00; Y10S148/028
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
135 words
A method for fabricating semiconductor devices comprising the steps of: a first step of forming a plurality of device areas having semiconductor devices formed therein and a scribing area separating each of said device areas from one another, wherein said device areas and said scribing area are formed on a semiconductor substrate; a second step of forming at least one of a plurality of mark patterns in said scribing area; and a third step, following said second step, of forming an edge cover on at least one of said plurality of mark patterns and said device patterns, such that each edge cover covers at least the peripheral portion of the mark pattern or device pattern and extends towards said scribing area beyond the edge of said mark pattern or device pattern, and contacts said substrate.
Claim 2
Independent Claim
135 words
A method for fabricating semiconductor devices comprising the steps of: a first step of forming a plurality of device areas having semiconductor devices formed therein and a scribing area separating each of said device areas from one another, wherein said device areas and said scribing area are formed on a semiconductor substrate; a second step of forming at least one of a plurality of mark patterns in said scribing area; and a third step, following said second step, of forming an edge cover on at least one of said plurality of mark patterns and said device patterns, such that each edge cover covers at least the peripheral portion of the mark pattern or device pattern and extends towards said scribing area beyond the edge of said mark pattern or device pattern, and contacts said substrate.
Claim 3
Dependent Claim
33 words
A method for fabricating semiconductor devices according to claim 1, wherein said second and third steps are repeated until all said mark patterns and said device patterns are provided with said edge covers.
Claim 4
Dependent Claim
89 words
A method for fabricating semiconductor devices according to claim 1 or 2, wherein: said second step comprises, a first substep of forming a first layer over said substrate, a second substep of forming at least one of said first mark patterns by patterning said first layer; and wherein said third step comprises, a third substep of forming a second layer over said substrate, and a fourth substep of forming said edge cover for at least one of said first mark patterns or device patterns, by patterning said second layer.
Claim 5
Dependent Claim
29 words
A method for fabricating semiconductor devices according to claim 3, wherein the substeps of said second and third steps are common with corresponding steps for forming said device areas.
Claim 6
Dependent Claim
46 words
A method for fabricating semiconductor devices according to claim 1, wherein said third step includes forming each of said edge covers so that the cover extends a distance of 1 to 10 μm on both sides of the edge of the mark patterns or device areas.
Claim 7
Dependent Claim
21 words
A method for fabricating semiconductor devices according to claim 1, wherein said edge cover is patterned by an anisotropic etching process.
Claim 8
Independent Claim
111 words
A method for fabricating semiconductor devices comprising the steps of: providing a semiconductor substrate having a plurality of device areas separated by a scribing area, each of the device areas having a step at an edge thereof; forming a film on the device areas and the scribing areas; and patterning said film by anisotropic etching to form a portion of semiconductor devices, said film being etched such that said film remains on the step of said device area and extends towards the device areas and the scribing area wherein a distance of extension on both sides exceeds a minimum distance required to prevent said film from being peeled off the step.
Claim 9
Independent Claim
111 words
A method for fabricating semiconductor devices comprising the steps of: providing a semiconductor substrate having a plurality of device areas separated by a scribing area, each of the device areas having a step at an edge thereof; forming a film on the device areas and the scribing areas; and patterning said film by anisotropic etching to form a portion of semiconductor devices, said film being etched such that said film remains on the step of said device area and extends towards the device areas and the scribing area wherein a distance of extension on both sides exceeds a minimum distance required to prevent said film from being peeled off the step.
References Cited (Backward Citations)
FR2282162A1
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US4179794A
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JPS5432067A
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US4306351A
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JPS5773933A
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JPS6016442A
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-07-21 | 1996-01-20 | 1996-07-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-07-21 | 2000-01-20 | 2000-07-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-07-21 | 2004-01-20 | 2004-07-21 | $7700.00 | Window Closed / Lapsed |