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US5622883A
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Method for manufacturing semiconductor memory device having landing pad
Assignee: Samsung Electronics Co Ltd
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Filing: 1995-10-30
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Granted: 1997-04-22
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Expires: 2015-10-30
Abstract
Abstract In manufacturing a high-integrated semiconductor memory device, there is disclosed a method for forming a trophy-shaped landing pad to a contact hole with a high aspect ratio by using a multiple-step etching process. According to the present invention, a storage node landing pad is formed by the multiple-step etching process and in different profiles via different etching processes from a bit line landing pad, thereby preventing a stringer or a bridge phenomenon occurring between the landing pads. Moreover, the trophy-shaped landing pad is formed by the multiple-step etching process, thereby securing an enough alignment margin and facilitating the manufacturing of 1 Gbit-grade DRAM by lowering the aspect ratio.
Inventors
- 👤 Jeong-Seok Kim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 13:54
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/09; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0144; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/081; H10W20/082
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
167 words
A method for manufacturing a semiconductor device having a landing pad for a storage electrode including the steps of: forming a first interlayer insulation film over a semiconductor substrate on which a transistor and a bit line landing pad are formed, the first interlayer insulation film covering the bit line landing pad and a gate of the transistor; sequentially etching the first interlayer insulation film to form a contact hole in the first interlayer insulation film using an isotropic wet etching method and using an anisotropic dry etching method; filling the contact hole with a first conductive material to form the storage electrode landing pad for connecting the storage electrode to a source/drain region of the transistor; planarizing the first conductive material using the first interlayer insulation film as a planarizing stopper to leave only the storage electrode landing pad in the contact hole; forming a bit line connected to the bit line landing pad; and forming the storage electrode connected to the storage electrode landing pad.
Claim 2
Independent Claim
167 words
A method for manufacturing a semiconductor device having a landing pad for a storage electrode including the steps of: forming a first interlayer insulation film over a semiconductor substrate on which a transistor and a bit line landing pad are formed, the first interlayer insulation film covering the bit line landing pad and a gate of the transistor; sequentially etching the first interlayer insulation film to form a contact hole in the first interlayer insulation film using an isotropic wet etching method and using an anisotropic dry etching method; filling the contact hole with a first conductive material to form the storage electrode landing pad for connecting the storage electrode to a source/drain region of the transistor; planarizing the first conductive material using the first interlayer insulation film as a planarizing stopper to leave only the storage electrode landing pad in the contact hole; forming a bit line connected to the bit line landing pad; and forming the storage electrode connected to the storage electrode landing pad.
Claim 3
Dependent Claim
39 words
A method for manufacturing a semiconductor device as claimed in claim 1, wherein etching profiles by the isotropic etching process have a tapered hemispherical shape with a depth of about 500-1,500 Å and a diameter of about 2,500-4,000 Å.
Claim 4
Dependent Claim
28 words
A method for manufacturing a semiconductor device as claimed in claim 1, wherein the first conductive material is selected from the group consisting of doped polycrystalline and tungsten.
Claim 5
Dependent Claim
33 words
A method for manufacturing a semiconductor device as claimed in claim 1, wherein the bit line landing pad and the storage electrode landing pad are formed at different heights by different etching methods.
Claim 6
Dependent Claim
23 words
A method for manufacturing a semiconductor device as claimed in claim 1, wherein the planarizing step is performed by an etching back method.
Claim 7
Dependent Claim
22 words
A method for manufacturing a semiconductor device as claimed in claim 1, wherein the planarizing step is performed by chemical mechanical polishing.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-04-21 | 2000-10-21 | 2001-04-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-04-21 | 2004-10-21 | 2005-04-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-04-21 | 2008-10-21 | 2009-04-22 | $7700.00 | Window Closed / Lapsed |