Communication system with link margin control and method

Claim 3

A method as claimed in claim 1 wherein said determining step comprises a step of integrating error magnitude.

Claim 4

A method as claimed in claim 2 wherein said detecting step comprises a step of counting that number of symbols over which said error magnitude is integrated.

Claim 5

A method as claimed in claim 1 wherein said controlling step comprises a step of evaluating programmable decision rules to decide whether to increase or decrease said power level, said data communication signal conveys error detection codes, and said method additionally comprises steps of: evaluating said error detection codes to measure bit error rate; and programming said decision rules in response to said measured bit error rate.

Claim 6

A method as claim in claim 1 wherein said controlling step increases said power level when said bit error rate estimate exceeds a value that varies in response to accuracy of said bit error rate estimate.

Claim 7

A method as claimed in claim 1 wherein said data communication signal is in the form of a data communication burst and said determining and detecting steps are performed approximately once for each burst.

Claim 10

A method as claimed in claim 7 wherein said determining step comprises steps of: accumulating said error magnitude values occurring in a predetermined sequence of symbols; and incrementing a counter for each of said symbols in which error magnitude values are accumulated.

Claim 11

A method as claimed in claim 8 wherein said determining step additionally comprises steps of: identifying a transfer time, said transfer time occurring when said counter indicates a value approximately equal to 2 N where N is an integer number; and recording, at said transfer time, accumulated error magnitude and a number corresponding to N.

Claim 12

A method as claimed in claim 9 wherein said deciding step comprises steps of: signifying an increase in said power level if said recorded accumulated error magnitude is greater than a threshold; and configuring said threshold so that said threshold divided by 2 N varies in response to N.

Claim 13

A method as claimed in claim 7 wherein said deciding step comprises a step of signifying an increase in said power level when said value divided by said number of symbols is greater than a decision point, said decision point varying in response to said number of symbols.

Claim 14

A method as claimed in claim 7 wherein said deciding step evaluates programmable decision rules, said data communication signal conveys error detection codes, and said method additionally comprises steps of: evaluating said error detection codes to measure a bit error rate; and programming said decision rules in response to said bit error rate.

Claim 15

A method as claimed in claim 7 wherein said data communication signal is in the form of a data communication burst and said deciding step occurs approximately once for each burst.

Claim 16

A method as claimed in claim 7 wherein: said data communication signal is in the form of a data communication burst that conveys a first number of symbols; and said determining and deciding steps are configured so that said number of symbols is less than or equal to said first number of symbols.

Claim 17

A method as claimed in claim 7 wherein said deciding step generates an instruction, and said method additionally comprises steps of: communicating said instruction to a transmission node; and adjusting said power level at said transmission node.

Claim 18

A data communication system that maintains a desired link margin, comprising: a first node having a transmitter configured to transmit a data communication signal at a programmable power level; a second node having an RF section configured to receive said data communication signal; a bit error rate estimator, coupled to said RF section, for generating a first parameter that corresponds to an estimate of a bit error rate for said data communication signal; an accuracy estimator, coupled to said RF section, for generating a second parameter that assesses accuracy of said first parameter; and a controller coupled to said bit error rate estimator and to said accuracy estimator, said controller being configured to program said programmable power level in response to said first and second parameters, wherein said controller is configured to program an increase in said power level when said bit error rate estimate exceeds a decision point that varies in response to the accuracy of said bit error rate estimate.

Claim 19

A data communication system that maintains a desired link margin, comprising: a first node having a transmitter configured to transmit a data communication signal at a programmable power level; a second node having an RF section configured to receive said data communication signal; a bit error rate estimator, coupled to said RF section, for generating a first parameter that corresponds to an estimate of a bit error rate for said data communication signal; an accuracy estimator, coupled to said RF section, for generating a second parameter that assesses accuracy of said first parameter; and a controller coupled to said bit error rate estimator and to said accuracy estimator, said controller being configured to program said programmable power level in response to said first and second parameters, wherein said controller is configured to program an increase in said power level when said bit error rate estimate exceeds a decision point that varies in response to the accuracy of said bit error rate estimate.

Claim 20

A data communication system as claimed in claim 16 wherein: said controller comprises means for storing decision rules that define when to adjust said power level; said decision rules are configured to increase said power level when said estimate of said bit error rate exceeds a first decision point and said second parameter assesses a first accuracy; and said decision rules are configured to increase said power level when said estimate of said bit error rate exceeds a second decision point and said second parameter assesses a second accuracy.

Claim 21

A data communication system as claimed in claim 16 wherein said controller is figured to program a decrease in said power level when said bit error rate estimate is less than a decision that varies in response to the accuracy of said bit error rate estimate.