Non-volatile dynamic random access memory

Claim 2

A semiconductor memory device including: memory means for storing data having volatile and non-volatile capability; access means for reading/writing the data stored in a volatile state at an address in said memory means in accordance with an access command indicating the address; transfer means for transferring the data stored in said memory means from the volatile state into a non-volatile state; and recall means for recalling the data stored in said memory means in the non-volatile state into the volatile state, wherein said recall means selectively performs a recall operation for a section of said memory means which includes the address before said access means performs a read/write operation for the data, when the data at the address is stored in the non-volatile state.

Claim 3

A semiconductor memory device including: memory means for storing data having volatile and non-volatile capability; access means for reading/writing the data stored in a volatile state at an address in said memory means in accordance with an access command indicating the address; transfer means for transferring the data stored in said memory means from the volatile state into a non-volatile state; recall means for recalling the data stored in said memory means in the non-volatile state into the volatile state; means for indicating if recall operation has been performed, after either supplying power to said semiconductor memory device or a last transfer operation has been performed; and means for controlling said access means and said recall means based on an indication of said indicating means, whereby in a case where said indication is positive, said access means performs a read/write operation for the data stored at the address, and in a case where said indication is negative, said recall means selectively performs a recall operation for a section of said memory means which includes the address before said access means performs a read/write operation for the data.

Claim 4

A semiconductor memory device including: memory means for storing data having volatile and non-volatile capability; access means for reading/writing the data stored in a volatile state at an address in said memory means in accordance with an access command indicating the address; transfer means for transferring the data stored in said memory means from the volatile state into a non-volatile state; recall means for recalling the data stored in said memory means in the non-volatile state into the volatile state; means for indicating if recall operation has been performed, after either supplying power to said semiconductor memory device or a last transfer operation has been performed; and means for controlling said access means and said recall means based on an indication of said indicating means, whereby in a case where said indication is positive, said access means performs a read/write operation for the data stored at the address, and in a case where said indication is negative, said recall means selectively performs a recall operation for a section of said memory means which includes the address before said access means performs a read/write operation for the data.

Claim 5

A semiconductor memory device according to claim 2, wherein said control means controls said transfer means whereby, in a case where said indication is negative for a first section of said memory means including the address and is positive for a second section of said memory means other than the first section, said transfer means performs a transfer operation for the data stored in at least a part of the second section.

Claim 6

A semiconductor memory device according to claim 3, wherein said transfer operation for the second section is performed during said recall operation for the first section is performed.

Claim 7

A semiconductor memory device according to claim 3, wherein said transfer operation for the second section is performed before or after said recall operation for the first section is performed.

Claim 8

A semiconductor memory device according to claim 3, wherein said control means controls said transfer means, whereby said transfer means performs the transfer operation when a total amount of addresses included in the second section is larger than a predetermined value.

Claim 9

A semiconductor memory device according to claim 2, including means for generating a wait signal, the wait signal being output at least during said recall means performs the recall operation.

Claim 10

A semiconductor memory device according to claim 2, including means for generating a store requiring signal for a section of said memory means, the store requiring signal being output in a case where said indication is positive for any address included in the section.

Claim 11

A semiconductor memory device according to claim 2, wherein said memory means includes a first portion for storing the data in a volatile manner and a second portion for storing the data in a non-volatile manner.

Claim 12

A semiconductor memory device according to claim 2, wherein said memory means includes a memory cell which changes the capability between volatile and non-volatile based on a voltage applied to said memory cell.

Claim 13

A semiconductor memory device according to claim 9, wherein said memory means includes a DRAM portion and an EEPROM portion.

Claim 14

A semiconductor memory device according to claim 10, wherein said memory cell includes a ferroelectric material.

Claim 15

A semiconductor memory device according to claim 3, including means for refreshing the data stored in the volatile state in the second section of said memory means, during said recalling means performs the recall operation for the first section.

Claim 16

A semiconductor memory device according to claim 13, further including: means for counting a number of refresh operations successively performed for an address by said refresh means; and means for controlling said transfer means based on the number of the refresh operations, whereby said transfer means performs the transfer operation for the address when the number is larger than a predetermined value.

Claim 17

A semiconductor memory device according to claim 14, wherein said counting means counts a number of the refresh operations performed after a last read/write operation is performed.

Claim 22

A method for driving a semiconductor memory device according to claim 17, wherein in a case where said indication is negative for a first section of said memory means including the address and positive for a second section of said memory means other than the first section, said transferring step is preformed for the data stored in at least a part of the second section.

Claim 23

A method for driving a semiconductor memory device according to claim 18, wherein said transfer step is performed for the second section during said recall step is performed for the first section.

Claim 24

A method for driving a semiconductor memory device according to claim 18, wherein said transfer step is performed for the second section before or after said recall operation is performed for the first section.

Claim 25

A method for driving a semiconductor memory device according to claim 18, wherein said transferring step is performed when a total amount of addresses included in the second section is larger than a predetermined value.

Claim 26

A method for driving a semiconductor memory device according to claim 17, further comprising the step of generating a wait signal, the wait signal being output at least during said recall means performs the recall operation.

Claim 27

A method for driving a semiconductor memory device according to claim 17, further comprising the step of generating a store requiring signal for a section of said memory means, the store requiring signal being output in a case where said indication is positive for any address included in the section.

Claim 28

A method for driving a semiconductor memory device according to claim 18, further including the step of refreshing the data stored in the volatile state in the second section of said memory means, during said recalling step is performed for the first section.

Claim 29

A method for driving a semiconductor memory device according to claim 20, further comprising the steps of: counting a number of successive refresh operations performed for an address in said refreshing step; and controlling said transferring step based on the number of the successive refresh operations, whereby said transferring step is performed for the address when the number is larger than a predetermined value.

Claim 30

A method for driving a semiconductor memory device according to claim 25, wherein said counting step is performed after a last read/write operation performed in said reading/writing step.