US5619468A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Two-stage memory refresh circuit
Assignee: GlobalFoundries Inc
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Filing: 1995-12-07
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Granted: 1997-04-08
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Expires: 2015-12-07
Abstract
Abstract A timing refresh circuit refreshes a timed circuit in a functionally equivalent manner, whether the timing refresh circuit is operated at a high frequency or a low frequency. The two-stage timing refresh circuit includes a counter and combinational logic, in combination, connected between a refresh timing signal generator and a control circuit. The counter is incremented for each refresh timing signal and decremented for each refresh cycle realized by the control circuit. The combinational logic converts the counter count to a refresh signal by generating a refresh request to the control circuit whenever a count is pending in the counter.
Inventors
- 👤 Atish Ghosh
- 👤 Jennifer B. Pencis
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 14:59
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
153 words
A timing control circuit for controlling timing signals to a fixed-timing circuit in a variable-time system, the fixed-timing circuit having an input terminal for receiving a timing signal and an output terminal for generating a timing signal indicative of fixed-timing circuit timing, the fixed-timing circuit being accessible to timing signals of the timing control circuit in a first state and inaccessible to timing signals of the timing control circuit in a second state, the timing control circuit comprising: a fixed timing signal generator; a counter having a first input terminal coupled to the fixed timing signal generator, a second input terminal coupled to the output terminal of the fixed-timing circuit and a plurality of output bit lines; and a combinational logic circuit having a plurality of input bit lines coupled to the plurality of output bit lines of the counter and an output line coupled to the input terminal of the fixed-timing circuit.
Claim 2
Dependent Claim
153 words
A timing control circuit for controlling timing signals to a fixed-timing circuit in a variable-time system, the fixed-timing circuit having an input terminal for receiving a timing signal and an output terminal for generating a timing signal indicative of fixed-timing circuit timing, the fixed-timing circuit being accessible to timing signals of the timing control circuit in a first state and inaccessible to timing signals of the timing control circuit in a second state, the timing control circuit comprising: a fixed timing signal generator; a counter having a first input terminal coupled to the fixed timing signal generator, a second input terminal coupled to the output terminal of the fixed-timing circuit and a plurality of output bit lines; and a combinational logic circuit having a plurality of input bit lines coupled to the plurality of output bit lines of the counter and an output line coupled to the input terminal of the fixed-timing circuit.
Claim 3
Dependent Claim
38 words
A timing control circuit according to claim 1, wherein: the counter is an up/down counter; the first input terminal of the counter is an up-count terminal; and the second input terminal of the counter is a down-count terminal.
Claim 4
Dependent Claim
49 words
A timing control circuit according to claim 1 wherein: the fixed-timing circuit is a DRAM circuit including a DRAM controller; the combinational logic circuit output line carries a refresh request signal; and the counter second input terminal is coupled to the DRAM circuit to receive a refresh cycle signal.
Claim 5
Dependent Claim
26 words
A timing control circuit according to claim 1 wherein: the combinational logic circuit is a multiple-input OR gate for selecting a selected count of the counter.
Claim 6
Dependent Claim
168 words
A timing refresh control circuit for controlling timing signals to a fixed-timing DRAM circuit in a variable-time system, the fixed-timing DRAM circuit having an input terminal for receiving a timing signal and an output terminal for generating a timing signal indicative of fixed-timing circuit timing, the fixed-timing DRAM circuit being accessible to timing signals of the timing refresh control circuit in a first state and inaccessible to timing signals of the timing refresh control circuit in a second state, the timing refresh control circuit comprising: a fixed timing refresh clock signal generator; a counter having a first input terminal coupled to the fixed timing refresh clock signal generator, a second input terminal coupled to the output terminal of the fixed-timing DRAM circuit and a plurality of output bit lines; and a combinational logic circuit having a plurality of input bit lines coupled to the plurality of output bit lines of the counter and a refresh cycle output line coupled to the input terminal of the fixed-timing DRAM circuit.
Claim 7
Dependent Claim
168 words
A timing refresh control circuit for controlling timing signals to a fixed-timing DRAM circuit in a variable-time system, the fixed-timing DRAM circuit having an input terminal for receiving a timing signal and an output terminal for generating a timing signal indicative of fixed-timing circuit timing, the fixed-timing DRAM circuit being accessible to timing signals of the timing refresh control circuit in a first state and inaccessible to timing signals of the timing refresh control circuit in a second state, the timing refresh control circuit comprising: a fixed timing refresh clock signal generator; a counter having a first input terminal coupled to the fixed timing refresh clock signal generator, a second input terminal coupled to the output terminal of the fixed-timing DRAM circuit and a plurality of output bit lines; and a combinational logic circuit having a plurality of input bit lines coupled to the plurality of output bit lines of the counter and a refresh cycle output line coupled to the input terminal of the fixed-timing DRAM circuit.
Claim 8
Dependent Claim
39 words
A timing refresh control circuit according to claim 5, wherein: the counter is an up/down counter; the first input terminal of the counter is an up-count terminal; and the second input terminal of the counter is a down-count terminal.
Claim 9
Dependent Claim
27 words
A timing refresh control circuit according to claim 5 wherein: the combinational logic circuit is a multiple-input OR gate for selecting a selected count of the counter.
Claim 10
Dependent Claim
158 words
A circuit board for operating at emulation speed in a first operating state and for operating at a circuit speed in a second operating state, the circuit board comprising: a fixed-timing circuit having an input terminal for receiving a timing signal and an output terminal for generating a timing signal indicative of fixed-timing circuit timing, the fixed-timing circuit being accessible to signals of the circuit board in a first state and inaccessible to timing signals of the circuit board in a second state; a fixed timing signal generator; a counter having a first input terminal coupled to the fixed timing signal generator, a second input terminal coupled to the output terminal of the fixed-timing circuit and a plurality of output bit lines; and a combinational logic circuit having a plurality of input bit lines coupled to the plurality of output bit lines of the counter and an output line coupled to the input terminal of the fixed-timing circuit.
Claim 11
Dependent Claim
158 words
A circuit board for operating at emulation speed in a first operating state and for operating at a circuit speed in a second operating state, the circuit board comprising: a fixed-timing circuit having an input terminal for receiving a timing signal and an output terminal for generating a timing signal indicative of fixed-timing circuit timing, the fixed-timing circuit being accessible to signals of the circuit board in a first state and inaccessible to timing signals of the circuit board in a second state; a fixed timing signal generator; a counter having a first input terminal coupled to the fixed timing signal generator, a second input terminal coupled to the output terminal of the fixed-timing circuit and a plurality of output bit lines; and a combinational logic circuit having a plurality of input bit lines coupled to the plurality of output bit lines of the counter and an output line coupled to the input terminal of the fixed-timing circuit.
Claim 12
Dependent Claim
37 words
A circuit board according to claim 8, wherein: the counter is an up/down counter; the first input terminal of the counter is an up-count terminal; and the second input terminal of the counter is a down-count terminal.
Claim 13
Dependent Claim
48 words
A circuit board according to claim 8 wherein: the fixed-timing circuit is a DRAM circuit including a DRAM controller; the combinational logic circuit output line carries a refresh request signal; and the counter second input terminal is coupled to the DRAM circuit to receive a refresh cycle signal.
Claim 14
Dependent Claim
25 words
A circuit board according to claim 8 wherein: the combinational logic circuit is a multiple-input OR gate for selecting a selected count of the counter.
Claim 15
Independent Claim
130 words
A method of controlling timing signals to a fixed-timing circuit in a variable-time system, the fixed-timing circuit having an input terminal for receiving a timing signal and an output terminal for generating a timing signal indicative of fixed-timing circuit timing, the fixed-timing circuit being accessible to timing signals in a first state and inaccessible to timing signals in a second state, the method comprising the steps of: generating a fixed timing signal; incrementing a count of the number of fixed timing signals; decrementing the count by the number of signals indicative of fixed-timing circuit timing; applying the fixed timing signal to the fixed-timing circuit when the count is greater than one; and terminating application of the fixed timing signal to the fixed-timing circuit when the count is decremented to zero.
Claim 16
Independent Claim
130 words
A method of controlling timing signals to a fixed-timing circuit in a variable-time system, the fixed-timing circuit having an input terminal for receiving a timing signal and an output terminal for generating a timing signal indicative of fixed-timing circuit timing, the fixed-timing circuit being accessible to timing signals in a first state and inaccessible to timing signals in a second state, the method comprising the steps of: generating a fixed timing signal; incrementing a count of the number of fixed timing signals; decrementing the count by the number of signals indicative of fixed-timing circuit timing; applying the fixed timing signal to the fixed-timing circuit when the count is greater than one; and terminating application of the fixed timing signal to the fixed-timing circuit when the count is decremented to zero.
Claim 17
Dependent Claim
41 words
A method according to claim 12 wherein: the fixed-timing circuit is a DRAM circuit including a DRAM controller; the fixed timing signal is a refresh request signal; and the timing signal indicative of fixed-timing circuit timing is a refresh cycle signal.
Claim 18
Independent Claim
161 words
A method of providing a timing control circuit for controlling timing signals to a fixed-timing circuit in a variable-time system, the fixed-timing circuit having an input terminal for receiving a timing signal and an output terminal for generating a timing signal indicative of fixed-timing circuit timing, the fixed-timing circuit being accessible to timing signals of the timing control circuit in a first state and inaccessible to timing signals of the timing control circuit in a second state, the method comprising the steps of: providing a fixed timing signal generator; providing a counter having a first input terminal coupled to the fixed timing signal generator, a second input terminal coupled to the output terminal of the fixed-timing circuit and a plurality of output bit lines; and providing a combinational logic circuit having a plurality of input bit lines coupled to the plurality of output bit lines of the counter and an output line coupled to the input terminal of the fixed-timing circuit.
Claim 19
Independent Claim
161 words
A method of providing a timing control circuit for controlling timing signals to a fixed-timing circuit in a variable-time system, the fixed-timing circuit having an input terminal for receiving a timing signal and an output terminal for generating a timing signal indicative of fixed-timing circuit timing, the fixed-timing circuit being accessible to timing signals of the timing control circuit in a first state and inaccessible to timing signals of the timing control circuit in a second state, the method comprising the steps of: providing a fixed timing signal generator; providing a counter having a first input terminal coupled to the fixed timing signal generator, a second input terminal coupled to the output terminal of the fixed-timing circuit and a plurality of output bit lines; and providing a combinational logic circuit having a plurality of input bit lines coupled to the plurality of output bit lines of the counter and an output line coupled to the input terminal of the fixed-timing circuit.
Claim 20
Dependent Claim
36 words
A method according to claim 14, wherein: the counter is an up/down counter; the first input terminal of the counter is an up-count terminal; and the second input terminal of the counter is a down-count terminal.
Claim 21
Dependent Claim
47 words
A method according to claim 14 wherein: the fixed-timing circuit is a DRAM circuit including a DRAM controller; the combinational logic circuit output line carries a refresh request signal; and the counter second input terminal is coupled to the DRAM circuit to receive a refresh cycle signal.
Claim 22
Dependent Claim
24 words
A method according to claim 14 wherein: the combinational logic circuit is a multiple-input OR gate for selecting a selected count of the counter.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-04-07 | 2000-10-07 | 2001-04-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-04-07 | 2004-10-07 | 2005-04-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-04-07 | 2008-10-07 | 2009-04-08 | $7700.00 | Window Closed / Lapsed |