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US5619448A
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Non-volatile memory device and apparatus for reading a non-volatile memory array
Assignee: Myson Tech Inc
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Filing: 1996-03-14
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Granted: 1997-04-08
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Expires: 2016-03-14
Abstract
Abstract A non-volatile memory array includes a plurality of memory cells. Each of the memory cells stores two-bits of data therein and has a threshold voltage corresponding to the data bits stored therein. A voltage providing unit provides a first test voltage to an addressed one of the memory cells. A sensing unit senses whether the addressed one of the memory cells is in a conducting state after the first test voltage has been applied thereto to determine a first bit of data stored therein. When the first bit of data stored in the addressed one of the memory cells is 0, the voltage providing unit provides a second test voltage and the sensing unit senses whether the addressed one of the memory cells is in the conducting state after the second test voltage has been applied thereto to determine a second bit of data stored therein. Otherwise, the voltage providing unit provides a third test voltage and the sensing unit senses whether the addressed one of the memory cells is in the conducting state after the third test voltage has been applied thereto to determine a second bit of data stored therein.
Inventors
- 👤 Yi-Pin Lin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 09:31
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/56; G11C11/5692; G11C11/5621; G11C11/5642
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
340 words
An apparatus for reading a non-volatile memory array, said memory array including a plurality of memory cells, each of the memory cells storing two-bits of data therein and being formed from one of first, second, third and fourth transistors, said first transistor having a first threshold voltage and corresponding to data bits 00, said second transistor having a second threshold voltage greater than the first threshold voltage and corresponding to data bits 01, said third transistor having a third threshold voltage greater than the second threshold voltage and corresponding to data bits 10, said fourth transistor having a fourth threshold voltage greater than the third threshold voltage and corresponding to data bits 11, said apparatus comprising: voltage providing means, adapted to be connected to the memory cells, for providing a first test voltage between the second and third threshold voltages to an addressed one of the memory cells; and sensing means, adapted to be connected to the memory cells and to said voltage providing means, for sensing whether the addressed one of the memory cells is in a conducting state after the first test voltage has been applied thereto to determine a first bit of data stored therein; when the first bit of data stored in said addressed one of the memory cells is 0, said sensing means controlling said voltage providing means to provide a second test voltage between the first and second threshold voltages and sensing whether said addressed one of the memory cells is in the conducting state after the second test voltage has been applied thereto to determine a second bit of data stored therein; when the first bit of data stored in said addressed one of the memory cells is 1, said sensing means controlling said voltage providing means to provide a third test voltage between the third and fourth threshold voltages and sensing whether said addressed one of the memory cells is in the conducting state after the third test voltage has been applied thereto to determine a second bit of data stored therein.
Claim 2
Independent Claim
340 words
An apparatus for reading a non-volatile memory array, said memory array including a plurality of memory cells, each of the memory cells storing two-bits of data therein and being formed from one of first, second, third and fourth transistors, said first transistor having a first threshold voltage and corresponding to data bits 00, said second transistor having a second threshold voltage greater than the first threshold voltage and corresponding to data bits 01, said third transistor having a third threshold voltage greater than the second threshold voltage and corresponding to data bits 10, said fourth transistor having a fourth threshold voltage greater than the third threshold voltage and corresponding to data bits 11, said apparatus comprising: voltage providing means, adapted to be connected to the memory cells, for providing a first test voltage between the second and third threshold voltages to an addressed one of the memory cells; and sensing means, adapted to be connected to the memory cells and to said voltage providing means, for sensing whether the addressed one of the memory cells is in a conducting state after the first test voltage has been applied thereto to determine a first bit of data stored therein; when the first bit of data stored in said addressed one of the memory cells is 0, said sensing means controlling said voltage providing means to provide a second test voltage between the first and second threshold voltages and sensing whether said addressed one of the memory cells is in the conducting state after the second test voltage has been applied thereto to determine a second bit of data stored therein; when the first bit of data stored in said addressed one of the memory cells is 1, said sensing means controlling said voltage providing means to provide a third test voltage between the third and fourth threshold voltages and sensing whether said addressed one of the memory cells is in the conducting state after the third test voltage has been applied thereto to determine a second bit of data stored therein.
Claim 3
Dependent Claim
43 words
An apparatus as claimed in claim 1, wherein said voltage providing means provides the first test voltage during a first half of a read cycle and provides either of the second and third test voltages during a second half of the read cycle.
Claim 4
Dependent Claim
341 words
A non-volatile memory device, comprising: a non-volatile memory array which includes a plurality of memory cells, each of the memory cells storing two-bits of data therein and being formed from one of first, second, third and fourth transistors, said first transistor having a first threshold voltage and corresponding to data bits 00, said second transistor having a second threshold voltage greater than the first threshold voltage and corresponding to data bits 01, said third transistor having a third threshold voltage greater than the second threshold voltage and corresponding to data bits 10, said fourth transistor having a fourth threshold voltage greater than the third threshold voltage and corresponding to data bits 11; and a reading apparatus including voltage providing means, adapted to be connected to the memory cells, for providing a first test voltage between the second and third threshold voltages to an addressed one of the memory cells, and sensing means, adapted to be connected to the memory cells and to said voltage providing means, for sensing whether the addressed one of the memory cells is in a conducting state after the first test voltage has been applied thereto to determine a first bit of data stored therein; when the first bit of data stored in said addressed one of said memory cells is 0, said sensing means controlling said voltage providing means to provide a second test voltage between the first and second threshold voltages and sensing whether said addressed one of said memory cells is in the conducting state after the second test voltage has been applied thereto to determine a second bit of data stored therein; when the first bit of data stored in said addressed one of said memory cells is 1, said sensing means controlling said voltage providing means to provide a third test voltage between the third and fourth threshold voltages and sensing whether said addressed one of the memory cells is in the conducting state after the third test voltage has been applied thereto to determine a second bit of data stored therein.
Claim 5
Dependent Claim
341 words
A non-volatile memory device, comprising: a non-volatile memory array which includes a plurality of memory cells, each of the memory cells storing two-bits of data therein and being formed from one of first, second, third and fourth transistors, said first transistor having a first threshold voltage and corresponding to data bits 00, said second transistor having a second threshold voltage greater than the first threshold voltage and corresponding to data bits 01, said third transistor having a third threshold voltage greater than the second threshold voltage and corresponding to data bits 10, said fourth transistor having a fourth threshold voltage greater than the third threshold voltage and corresponding to data bits 11; and a reading apparatus including voltage providing means, adapted to be connected to the memory cells, for providing a first test voltage between the second and third threshold voltages to an addressed one of the memory cells, and sensing means, adapted to be connected to the memory cells and to said voltage providing means, for sensing whether the addressed one of the memory cells is in a conducting state after the first test voltage has been applied thereto to determine a first bit of data stored therein; when the first bit of data stored in said addressed one of said memory cells is 0, said sensing means controlling said voltage providing means to provide a second test voltage between the first and second threshold voltages and sensing whether said addressed one of said memory cells is in the conducting state after the second test voltage has been applied thereto to determine a second bit of data stored therein; when the first bit of data stored in said addressed one of said memory cells is 1, said sensing means controlling said voltage providing means to provide a third test voltage between the third and fourth threshold voltages and sensing whether said addressed one of the memory cells is in the conducting state after the third test voltage has been applied thereto to determine a second bit of data stored therein.
Claim 6
Dependent Claim
17 words
A non-volatile memory device as claimed in claim 3, wherein said memory cells are connected in parallel.
Claim 7
Dependent Claim
17 words
A non-volatile memory device as claimed in claim 3, wherein said memory cells are connected in series.
Claim 8
Dependent Claim
45 words
A non-volatile memory device as claimed in claim 3, wherein said voltage providing means provides the first test voltage during a first half of a read cycle and provides either of the second and third test voltages during a second half of the read cycle.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-04-07 | 2000-10-07 | 2001-04-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-04-07 | 2004-10-07 | 2005-04-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-04-07 | 2008-10-07 | 2009-04-08 | $7700.00 | Window Closed / Lapsed |