US5619408A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and system for recoding noneffective instructions within a data processing system
Assignee: International Business Machines Corp
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Filing: 1995-02-10
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Granted: 1997-04-08
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Expires: 2015-02-10
Abstract
Abstract A method and system are disclosed for processing instructions within a data processing system including a processor having a plurality of execution units. According to the method of the present invention, a number of instructions stored within a memory within the data processing system are retrieved from memory. A selected instruction among the number of instructions is decoded to determine if the selected instruction would be noneffective if executed by the processor. In a preferred embodiment of the present invention, noneffective instructions include instructions with invalid opcodes and instructions that would not change the value of any data register within the processor. In response to determining that the selected instruction would be noneffective if executed by the processor, the selected instruction is recoded into a specified instruction format prior to dispatching the selected instruction to one of the number of execution units. Detecting noneffective instructions prior to dispatch reduces the decode logic required within the dispatcher and enhances processor performance.
Inventors
- 👤 Bryan Black
- 👤 Marvin A. Denman
- 👤 Lee E. Eisen
- 👤 Robert T. Golla
- 👤 Albert J. Loper, Jr.
- 👤 Soummya Mallick
- 👤 Russell A. Reininger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 18:07
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/3017; G06F9/30145; G06F9/30181
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
137 words
A method within a data processing system of processing instructions prior to execution by a processor including at least one execution unit, wherein instructions are stored within a memory within said data processing system, said method comprising: retrieving a plurality of instructions from said memory; decoding a selected instruction among said plurality of instructions to determine if execution of said selected instruction would alter data stored within one of a plurality of data registers within said processor; in response to a determination that execution of said selected instruction would not alter data stored within one of said plurality of data registers within said processor, recoding said selected instruction into a first instruction format prior to dispatching said selected instruction to said at least one execution unit; and thereafter, discarding said selected instruction in said first instruction format.
Claim 2
Independent Claim
137 words
A method within a data processing system of processing instructions prior to execution by a processor including at least one execution unit, wherein instructions are stored within a memory within said data processing system, said method comprising: retrieving a plurality of instructions from said memory; decoding a selected instruction among said plurality of instructions to determine if execution of said selected instruction would alter data stored within one of a plurality of data registers within said processor; in response to a determination that execution of said selected instruction would not alter data stored within one of said plurality of data registers within said processor, recoding said selected instruction into a first instruction format prior to dispatching said selected instruction to said at least one execution unit; and thereafter, discarding said selected instruction in said first instruction format.
Claim 3
Dependent Claim
26 words
The method of processing instructions of claim 1, wherein said step of decoding said selected instruction comprises determining if said selected instruction has an invalid opcode.
Claim 4
Dependent Claim
40 words
The method of processing instructions of claim 2, wherein said processor includes a completion buffer, said method further comprising: in response to said determination that said selected instruction has an invalid opcode, dispatching said selected instruction to said completion buffer.
Claim 5
Dependent Claim
39 words
The method of processing instructions of claim 2, and further comprising: in response to a determination that said selected instruction has an invalid opcode, recoding said selected instruction into a second instruction format prior to dispatching said selected instruction.
Claim 6
Dependent Claim
33 words
The method of processing instructions of claim 4, and further comprising: subsequent to said step of recoding said selected instruction into said second instruction format, storing said selected instruction within an instruction cache.
Claim 7
Dependent Claim
28 words
The method of processing instructions of claim 5, and further comprising: thereafter, dispatching said selected instruction in said second instruction format to said at least one execution unit.
Claim 8
Dependent Claim
167 words
A data processing system, said data processing system comprising: at least one execution unit that performs data processing operations specified by instructions input to said at least one execution unit; a plurality of data registers; a first portion of memory which that stores instructions that may be executed by said at least one execution unit; means for retrieving a plurality of instructions from said first portion of memory; decoding logic, coupled to said means for retrieving, which detects if execution of a selected instruction among said plurality of instructions retrieved from said memory would alter data stored within one of said plurality of data registers; recoding logic, which in response to a detection that execution of said selected instruction would not alter data stored within one of said plurality of data registers, recodes said selected instruction into a first instruction format prior to dispatching said selected instruction to said at least one execution unit; and discarding logic that discards said selected instruction in said first instruction format.
Claim 9
Dependent Claim
167 words
A data processing system, said data processing system comprising: at least one execution unit that performs data processing operations specified by instructions input to said at least one execution unit; a plurality of data registers; a first portion of memory which that stores instructions that may be executed by said at least one execution unit; means for retrieving a plurality of instructions from said first portion of memory; decoding logic, coupled to said means for retrieving, which detects if execution of a selected instruction among said plurality of instructions retrieved from said memory would alter data stored within one of said plurality of data registers; recoding logic, which in response to a detection that execution of said selected instruction would not alter data stored within one of said plurality of data registers, recodes said selected instruction into a first instruction format prior to dispatching said selected instruction to said at least one execution unit; and discarding logic that discards said selected instruction in said first instruction format.
Claim 10
Dependent Claim
25 words
The data processing system of claim 7, and further comprising: an instruction cache for storing instructions among said plurality of instructions that are not discarded.
Claim 11
Dependent Claim
23 words
The data processing system of claim 7, wherein said decoding logic includes means for determining if said selected instruction has an invalid opcode.
Claim 12
Dependent Claim
40 words
The data processing system of claim 9, and further comprising: a completion buffer for storing completed instructions; and means, responsive to said determination that said selected instruction has an invalid opcode, for dispatching said selected instruction to said completion buffer.
Claim 13
Dependent Claim
34 words
The data processing system of claim 9, and further comprising: recoding logic, responsive to a determination that said selected instruction has an invalid opcode, for recoding said selected instruction into a second instruction format.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-04-07 | 2000-10-07 | 2001-04-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-04-07 | 2004-10-07 | 2005-04-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-04-07 | 2008-10-07 | 2009-04-08 | $7700.00 | Window Closed / Lapsed |