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JPS60103450A Expired / Lapsed JP ⏱️ 0.0 years remaining

Microprogram control system

Assignee: Fujitsu Ltd
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Filing: 1983-11-10
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Granted: —
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Expires: 2003-11-10
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Abstract

Abstract PURPOSE:To execute a non-operation (NOP) instruction with a microprogram without increasing the capacity of a control memory, by inserting the NOP instruction for timing control to a data register of the control memory at a desired time point. CONSTITUTION:A microprogram address obtained by decoding the operation part of a microinstruction is set to a control memory address register 1 through a next address control circuit 4. An access is given to a control memory 2, and the microinstruction is read out to a data register 3. Then this read-out instruction is decoded by a decoder 7 and latched by a controller 8 for execution of an instruction action. In this case, an NOP control field 31 is decoded by a decoder 5 and then latched by an NOP command insertion control latch 6 after it is detected that the insertion of an NOP instruction is indicated in the next machine cycle. The output NOPC of the latch 6 controls a selection circuit 21, and the NOP code is set to the operation part of the register 3. Then the NOP instruction is executed and the next address of the register 1 is executed.

Inventors

  • 👤 Hisajiro Sagara
  • 👤 相良 久次郎
  • 👤 Koichi Inoue
  • 👤 浩一 井上
  • 👤 Katsuyuki Iwata
  • 👤 勝行 岩田

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-07 17:13
CPC Classifications
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