Patent US5617431A successfully refreshed from Google Patents.
US5617431A
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Method and apparatus to reuse existing test patterns to test a single integrated circuit containing previously existing cores
Assignee: Advanced Micro Devices Inc
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Filing: 1994-08-02
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Granted: 1997-04-01
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Expires: 2014-08-02
Abstract
Abstract Test vectors are applied to a single integrated circuit containing at least one logic core for which a preexisting test vector set exists. Each test vector ordinarily applied in one cycle to test a core by itself, is converted into a first and second test vector. The first test vector is applied to input pins of the single integrated circuit during a first time period. Test registers connected to the input pins of the integrated circuit are loaded with signal values from the first test vector. The test registers are loaded according to a load signal. The test registers are connected between the input pins and a first set of drivers, the drivers being connected to the logic core under test. The second test vector is applied through the input pins to a second set of drivers during a second time period. A test mode signal is provided from a test interface to control the drivers. The signals stored in the test registers are provided concurrently with the signals applied to the input pins of the integrated circuit during the second time period to the logic core under test through the first and second drivers respectively.
Inventors
- 👤 Raghuram S. Tupuri
- 👤 Harikumar B. Nair
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 10:09
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3183; G01R31/318392; G01R31/318307; G01R31/3185; G01R31/318533; G01R31/318544; G01R31/318505
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
200 words
A method of applying test vectors to a single integrated circuit containing at least one logic core for which a preexisting test vector set exists, the test vector set having a plurality of test vectors normally applied in one cycle, the method comprising the steps of: (a) converting each test vector of the test vector set into a first and second test vector; (b) applying the first test vector to input pins of the single integrated circuit during a first time period; (c) loading a test register connected to one of the input pins with a signal value from the first test vector, the test register being connected between the one input pin and a logic core under test; (d) applying the second test vector to the input pins during a second time period; (e) providing to the logic core under test the signal value stored in the test register concurrently with a signal value from the second test vector applied to the one input pin during the second time period; (f) observing the results; and repeating steps (b) through (f) for each test vector until the logic core is tested with each test vector in the test vector set.
Claim 2
Independent Claim
200 words
A method of applying test vectors to a single integrated circuit containing at least one logic core for which a preexisting test vector set exists, the test vector set having a plurality of test vectors normally applied in one cycle, the method comprising the steps of: (a) converting each test vector of the test vector set into a first and second test vector; (b) applying the first test vector to input pins of the single integrated circuit during a first time period; (c) loading a test register connected to one of the input pins with a signal value from the first test vector, the test register being connected between the one input pin and a logic core under test; (d) applying the second test vector to the input pins during a second time period; (e) providing to the logic core under test the signal value stored in the test register concurrently with a signal value from the second test vector applied to the one input pin during the second time period; (f) observing the results; and repeating steps (b) through (f) for each test vector until the logic core is tested with each test vector in the test vector set.
Claim 3
Dependent Claim
60 words
The method according to claim 1 further comprising the step of providing a test mode signal to a first driver connected between the test register and the logic core under test and providing the test mode signal to a second driver connected between the one input pin and the logic core under test to enable the first and second drivers.
Claim 4
Dependent Claim
33 words
The method according to claim 1, further comprising the step of providing a load signal to the test register to load the test register with the signal value from the one input pin.
Claim 5
Dependent Claim
47 words
The method according to claim 1 further comprising the step of reconfiguring a pin of the single integrated circuit as a test pin and providing the load signal through the test pin, the test pin being reconfigured according to a test signal supplied from a test interface.
Claim 6
Dependent Claim
183 words
The method according to claim 1, further comprising the steps of: (g) converting each test vector of a second test vector set previously created to be applied in one cycle to a second logic core under test, into a third and a fourth test vector; (h) applying the third test vector to input pins of the single integrated circuit during a third time period; (i) loading a second test register connected to another of the input pins with a signal value from the third test vector, the second test register being connected between the other input pin and the second logic core under test; (j) applying the fourth test vector to the input pins during a fourth time period; (k) providing the signal value stored in the second test register concurrently with a signal value from the fourth test vector applied to the other input pin during the fourth time period, to the second logic core under test; (l) observing the results; and repeating steps (h) through (l) until the entire converted second test vector set is applied to the second logic core.
Claim 7
Dependent Claim
35 words
The method according to claim 5, further comprising the step of providing a load signal to the second test register to load the second test register with the signal value of the third test vector.
Claim 8
Dependent Claim
17 words
The method according to claim 2, wherein the test mode signal is provided from a test interface.
Claim 9
Dependent Claim
16 words
The method according to claim 7, wherein the test interface is a JTAG test access port.
Claim 10
Dependent Claim
65 words
The method according to claim 5 further comprising the step of providing a second test mode signal to a third driver connected between the second test register and the second logic core under test and providing the second test mode signal to a fourth driver connected between the other input pin and the second logic core under test to enable the third and fourth drivers.
Claim 11
Independent Claim
132 words
A method of applying test vectors to a single integrated circuit containing a logic core under test, the method comprising the steps of: (a) dividing a test vector into a first test vector and a second test vector; (b) applying the first test vector to specific input pins of the integrated circuit during a first time period; (c) loading test registers connected to respective ones of the specific input pins with the first test vector; (d) applying the second test vector to input pins of the integrated circuit, including the specific input pins, during a second time period; and (e) providing to the logic core under test, the first test vector stored in the test registers concurrently with the second test vector applied to the input pins during the second time period.
Claim 12
Independent Claim
132 words
A method of applying test vectors to a single integrated circuit containing a logic core under test, the method comprising the steps of: (a) dividing a test vector into a first test vector and a second test vector; (b) applying the first test vector to specific input pins of the integrated circuit during a first time period; (c) loading test registers connected to respective ones of the specific input pins with the first test vector; (d) applying the second test vector to input pins of the integrated circuit, including the specific input pins, during a second time period; and (e) providing to the logic core under test, the first test vector stored in the test registers concurrently with the second test vector applied to the input pins during the second time period.
Claim 13
Dependent Claim
35 words
The method according to claim 10, wherein the test registers are respectively connected between the specific input pins and a set of first drivers, the first drivers being connected to the logic core under test.
Claim 14
Dependent Claim
30 words
The method according to claim 11, wherein at least a portion of the second test vector is supplied to the logic core under test through a second set of drivers.
Claim 15
Dependent Claim
34 words
The method according to claim 12, wherein the first and second set of drivers are enabled according to a test mode signal supplied from a test interface connected to the first and second drivers.
Claim 16
Independent Claim
137 words
An apparatus for applying test vectors to a single integrated circuit containing a logic core under test, comprising: a circuit to divide a test vector into a first test vector and a second test vector; a plurality of test registers connected to respective ones of specific input pins of the integrated circuit, the test registers storing the first test vector applied to the specific input pins during a first time period; and a plurality of first drivers connected between the test registers and the logic core under test; wherein a test control signal is connected to the first drivers to enable the first drivers, thereby simultaneously applying the first test vector stored in the test registers and the second test vector supplied from the input pins during a second time period, to the logic core under test.
Claim 17
Independent Claim
137 words
An apparatus for applying test vectors to a single integrated circuit containing a logic core under test, comprising: a circuit to divide a test vector into a first test vector and a second test vector; a plurality of test registers connected to respective ones of specific input pins of the integrated circuit, the test registers storing the first test vector applied to the specific input pins during a first time period; and a plurality of first drivers connected between the test registers and the logic core under test; wherein a test control signal is connected to the first drivers to enable the first drivers, thereby simultaneously applying the first test vector stored in the test registers and the second test vector supplied from the input pins during a second time period, to the logic core under test.
Claim 18
Dependent Claim
38 words
The apparatus as recited in claim 14 further comprising a plurality of second drivers connected between input pins of the integrated circuit and the logic core under test, said second drivers being connected to said test control signal.
Claim 19
Dependent Claim
42 words
The apparatus as recited in claim 14, further comprising a load test register signal supplied to the test registers to control loading of the test registers, the load test register signal being supplied from a test input pin of the integrated circuit.
Claim 20
Dependent Claim
31 words
The apparatus as recited in claim 16, further comprising means for reconfiguring a pin of the integrated circuit as the test input pin, according to a signal from a test interface.
Claim 21
Dependent Claim
43 words
The apparatus as recited in claim 14, further comprising: a test access port accessed through input and output pins of the integrated circuit; and a register supplying the test control signal, a value of the register being controlled by the test access port.
Claim 22
Independent Claim
161 words
A method of applying test vectors to a single integrated circuit containing at least one logic core under test, the method comprising the steps of: (a) dividing a test vector into first to N-1 (N being an integer greater than or equal to 2) test vectors and an Nth test vector; (b) applying the first to N-1 test vectors to input pins of the integrated circuit during a first to N-1 time period, respectively; (c) loading a first to N-1 set of test registers connected to respective ones of the input pins with the first to N-1 test vectors during the first to N-1 time periods, respectively; (d) applying the Nth test vector to input pins of the integrated circuit, during an Nth time period; and (e) providing to the logic core under test, the first through N-1 test vectors stored in the test registers concurrently with the Nth test vector applied to the input pins during the Nth time period.
Claim 23
Independent Claim
161 words
A method of applying test vectors to a single integrated circuit containing at least one logic core under test, the method comprising the steps of: (a) dividing a test vector into first to N-1 (N being an integer greater than or equal to 2) test vectors and an Nth test vector; (b) applying the first to N-1 test vectors to input pins of the integrated circuit during a first to N-1 time period, respectively; (c) loading a first to N-1 set of test registers connected to respective ones of the input pins with the first to N-1 test vectors during the first to N-1 time periods, respectively; (d) applying the Nth test vector to input pins of the integrated circuit, during an Nth time period; and (e) providing to the logic core under test, the first through N-1 test vectors stored in the test registers concurrently with the Nth test vector applied to the input pins during the Nth time period.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-03-31 | 2000-09-30 | 2001-04-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-03-31 | 2004-09-30 | 2005-04-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-03-31 | 2008-09-30 | 2009-04-01 | $7700.00 | Window Closed / Lapsed |