Power transistor module wiring structure

Claim 2

A power transistor module comprising: a circuit substrate; at least one pair of power transistor chips on the circuit substrate, respectively comprising a first (Tr1) and a second (Tr2) power transistor electrically interconnected in series as upper and lower arms of a bridge circuit; first (D1) and second (D2) freewheel diodes connected antiparallel to the first (Tr1) and second (Tr2) power transistor, respectively; separate first and second circuit patterns on the circuit substrate for the respective first (Tr1) and second (Tr2) power transistors, the first circuit pattern comprising a first emitter pattern and the second circuit pattern comprising a second collector pattern; first (C1), second (C2E1) and third (E2) output terminals, and first (G1) and second (G2) gate terminals taken out from the first and second circuit patterns; a bridge shaped internal connecting terminal interconnecting the first emitter pattern and the second collector pattern; and a signal terminal (e1) connected to the internal connecting terminal as an auxiliary emitter terminal, at a point at which a desired internal wiring inductance is provided between the internal connecting terminal and the first emitter pattern.

Claim 3

The power transistor module according to claim 1, wherein the internal connecting terminal is loosely supported to allow its movement by a terminal block.

Claim 4

The power transistor module according to claim 1, further comprising an encapsulation, and gel filling material in which the internal connecting terminal is buried.

Claim 5

The power transistor module according to claim 1, wherein the respective freewheel diodes (D1 and D2) are on the same respective circuit patterns as the power transistors (Tr1 and Tr2).

Claim 6

A power transistor module comprising: a circuit substrate; at least one pair of power transistor chips on the circuit substrate, respectively comprising a first (Tr1) and a second (Tr2) power transistor electrically interconnected in series as upper and lower arms of a bridge circuit, and packaged as a minimum circuit; first (D1) and second (D2) freewheel diodes connected antiparallel to the first (Tr1) and second (Tr2) power transistor, respectively; a first collector pattern for the first power transistor a circuit pattern on the circuit substrate, comprising a first emitter pattern for the first power transistor (Tr1) connected to a second collector pattern for the second power transistor (Tr2); a second emitter pattern for the second power transistor (Tr2) on the circuit substrate; first and second gate patterns for the first and second power transistors on the circuit substrate; first (C1), second (C2E1) and third (E2) output terminals taken out from the first collector pattern, the circuit pattern and the second emitter pattern, respectively; first (G1) and second (G2) gate terminals taken out from the first and second gate patterns, respectively; an inductance providing region in a current path of one of the emitter patterns the current path having a width, and a slit dividing the width, forming the inductance providing region; and signal terminals (e1 and e2) as auxiliary emitter terminals for each of the power transistors (Tr1 and Tr2), a first one of said signal terminals connected to the inductance providing region at a point at which a desired internal wiring inductance is provided.

Claim 7

A power transistor module comprising: a circuit substrate; at least one pair of power transistor chips on the circuit substrate, respectively comprising a first (Tr1) and a second (Tr2) power transistor electrically interconnected in series as upper and lower arms of a bridge circuit, and packaged as a minimum circuit; first (D1) and second (D2) freewheel diodes connected antiparallel to the first (Tr1) and second (Tr2) power transistor, respectively; a first collector pattern for the first power transistor a circuit pattern on the circuit substrate, comprising a first emitter pattern for the first power transistor (Tr1) connected to a second collector pattern for the second power transistor (Tr2); a second emitter pattern for the second power transistor (Tr2) on the circuit substrate; first and second gate patterns for the first and second power transistors on the circuit substrate; first (C1), second (C2E1) and third (E2) output terminals taken out from the first collector pattern, the circuit pattern and the second emitter pattern, respectively; first (G1) and second (G2) gate terminals taken out from the first and second gate patterns, respectively; an inductance providing region in a current path of one of the emitter patterns the current path having a width, and a slit dividing the width, forming the inductance providing region; and signal terminals (e1 and e2) as auxiliary emitter terminals for each of the power transistors (Tr1 and Tr2), a first one of said signal terminals connected to the inductance providing region at a point at which a desired internal wiring inductance is provided.

Claim 8

The power transistor module according to claim 5, wherein the respective freewheel diodes (D1 and D2) are on the same respective collector patterns as the power transistors (Tr1 and Tr2).

Claim 9

A power transistor module comprising: a circuit substrate; at least one pair of power transistor chips on the circuit substrate, respectively comprising a first (Tr1) and a second (Tr2) power transistor electrically interconnected in series as upper and lower arms of a bridge circuit, and packaged as a minimum circuit; first (D1) and second (D2) freewheel diodes connected antiparallel to the first (Tr1) and second (Tr2) power transistor, respectively; a first collector pattern for the first power transistor (TE1) on the circuit substrate; a circuit pattern on the circuit substrate, comprising a first emitter pattern for the first power transistor (Tr1) connected to a second collector pattern for the second power transistor (Tr2); a second emitter pattern for the second power transistor (Tr2) on the circuit substrate; first and second gate patterns for the first and second power transistors on the circuit substrate; first (C1), second (C2E1) and third (E2) output terminals taken out from the first collector pattern, the circuit pattern and the second emitter pattern, respectively; first (G1) and second (G2) gate terminals taken out from the first and second gate patterns, respectively; an inductance providing region in a current path of one of the emitter patterns; signal terminals (e1 and e2) as auxiliary emitter terminals for each of the power transistors (Tr1 and Tr2), a first one of said signal terminals connected to the inductance providing region at a point at which a desired internal wiring inductance is provided; and marks along the inductance providing region indicating positions for connecting said first one of the signal terminals (e1 and e2).

Claim 10

A power transistor module comprising: a circuit substrate; at least one pair of power transistor chips on the circuit substrate, respectively comprising a first (Tr1) and a second (Tr2) power transistor electrically interconnected in series as upper and lower arms of a bridge circuit, and packaged as a minimum circuit; first (D1) and second (D2) freewheel diodes connected antiparallel to the first (Tr1) and second (Tr2) power transistor, respectively; a first collector pattern for the first power transistor (TE1) on the circuit substrate; a circuit pattern on the circuit substrate, comprising a first emitter pattern for the first power transistor (Tr1) connected to a second collector pattern for the second power transistor (Tr2); a second emitter pattern for the second power transistor (Tr2) on the circuit substrate; first and second gate patterns for the first and second power transistors on the circuit substrate; first (C1), second (C2E1) and third (E2) output terminals taken out from the first collector pattern, the circuit pattern and the second emitter pattern, respectively; first (G1) and second (G2) gate terminals taken out from the first and second gate patterns, respectively; an inductance providing region in a current path of one of the emitter patterns; signal terminals (e1 and e2) as auxiliary emitter terminals for each of the power transistors (Tr1 and Tr2), a first one of said signal terminals connected to the inductance providing region at a point at which a desired internal wiring inductance is provided; and marks along the inductance providing region indicating positions for connecting said first one of the signal terminals (e1 and e2).

Claim 11

The power transistor module according to claim 7, wherein the respective freewheel diodes (D1 and D2) are on the same respective collector patterns as the power transistors (Tr1 and Tr2).