Low voltage one transistor flash EEPROM cell using Fowler-Nordheim programming and erase

Claim 1

A method of identifying over-erased cells in an electrically erasable and programmable device of the type having a plurality of cells each comprising a single transistor having a source, a drain, a control gate, and a floating gate positioned between the control gate and the source and drain, and further of the type having a plurality of row address lines each coupled to the control gates of the cells in an associated row, a plurality of column address lines each coupled to the drains of the cells in an associated column, and a plurality of source lines coupled to the sources of the cells, the method comprising the steps of: (a) separately testing each column for the presence of over-erased cells; and (b) individually testing the cells in columns found to have over-erased cells to determine which cells are over-erased, including the steps of (i) selecting a cell to be tested, and (ii) raising the sources of all cells within said column to a potential which biases cells in said column, which cells are over-erased but are not selected, into a non-conducting state.

Claim 2

A method of identifying over-erased cells in an electrically erasable and programmable device of the type having a plurality of cells each comprising a single transistor having a source, a drain, a control gate, and a floating gate positioned between the control gate and the source and drain, and further of the type having a plurality of row address lines each coupled to the control gates of the cells in an associated row, a plurality of column address lines each coupled to the drains of the cells in an associated column, and a plurality of source lines coupled to the sources of the cells, the method comprising the steps of: (a) separately testing each column for the presence of over-erased cells; and (b) individually testing the cells in columns found to have over-erased cells to determine which cells are over-erased, including the steps of (i) selecting a cell to be tested, and (ii) raising the sources of all cells within said column to a potential which biases cells in said column, which cells are over-erased but are not selected, into a non-conducting state.

Claim 4

A method of identifying over-erased cells in an electrically erasable and programmable device of the type having a plurality of cells each comprising a single transistor having a source, a drain, a control gate, and a floating gate positioned between the control gate and the source and drain, and further of the type having a plurality of row address lines each coupled to the control gates of the cells in an associated row, a plurality of column address lines each coupled to the drains of the cells in an associated column, and a plurality of source lines coupled to the sources of the cells, the method comprising the steps of: (a) separately testing each column for the presence of over-erased cells including the steps of: (i) placing the cells in each column in a predetermined electrical condition which includes the steps of (1) applying a voltage of approximately 1.2 volts to the column address line associated with each column, (2) applying a voltage of approximately 0.6 volts to the source lines associated with the cells in each column, and (3) applying a voltage in a range of approximately 0 volts to approximately 2.0 volts to the row address lines associated with the cells in each column (ii) reading the cells in each column in a simultaneous read operation; and (iii) determining whether current is flowing into each column which, when the cells are in the predetermined electrical condition, is an indication that over-erased cells are present in the column; and (b) individually testing the cells in columns found to have over-erased cells to determine which cells are over-erased, including the steps of (i) selecting a cell to be tested, and (ii) raising the sources of all cells within said column to a potential which biases cells in said column, which cells are over-erased but are not selected, into a non-conducting state.

Claim 5

A method of identifying over-erased cells in an electrically erasable and programmable device of the type having a plurality of cells each comprising a single transistor having a source, a drain, a control gate, and a floating gate positioned between the control gate and the source and drain, and further of the type having a plurality of row address lines each coupled to the control gates of the cells in an associated row, a plurality of column address lines each coupled to the drains of the cells in an associated column, and a plurality of source lines coupled to the sources of the cells, the method comprising the steps of: (a) separately testing each column for the presence of over-erased cells including the steps of: (i) placing the cells in each column in a predetermined electrical condition which includes the steps of (1) applying a voltage of approximately 1.2 volts to the column address line associated with each column, (2) applying a voltage of approximately 0.6 volts to the source lines associated with the cells in each column, and (3) applying a voltage in a range of approximately 0 volts to approximately 2.0 volts to the row address lines associated with the cells in each column (ii) reading the cells in each column in a simultaneous read operation; and (iii) determining whether current is flowing into each column which, when the cells are in the predetermined electrical condition, is an indication that over-erased cells are present in the column; and (b) individually testing the cells in columns found to have over-erased cells to determine which cells are over-erased, including the steps of (i) selecting a cell to be tested, and (ii) raising the sources of all cells within said column to a potential which biases cells in said column, which cells are over-erased but are not selected, into a non-conducting state.

Claim 7

A method of identifying over-erased cells in an electrically erasable and programmable device of the type having a plurality of cells each comprising a single transistor having a source, a drain, a control gate, and a floating gate positioned between the control gate and the source and drain, and further of the type having a plurality of row address lines each coupled to the control gates of the cells in an associated row, a plurality of column address lines each coupled to the drains of the cells in an associated column, and a plurality of source lines coupled to the sources of the cells, the method comprising the steps of: (a) separately testing each column for the presence of over-erased cells; and (b) individually testing the cells in columns found to have over-erased cells to determine which cells are over-erased, including the steps of (i) selecting a cell to be tested, and (ii) raising the sources of all cells within said column to a potential which biases cells in said column, which cells are over-erased but are not selected, into a non-conducting state, (iii) placing the selected cell in a predetermined electrical condition, which includes the steps of (1) applying a voltage of approximately 1.2 volts to the column address line associated with the cell, (2) applying a voltage of approximately 0.6 volts to the source line associated with the cell, and (3) applying voltages in a range of approximately 0 volts to approximately 2.0 volts to the row address line associated with the cell; (iv) reading the selected cell in a read operation; and (v) determining whether current is flowing into the selected cell which, when a cell is in the predetermined electrical. Condition, is an indication that it is over-erased.

Claim 8

A method of identifying over-erased cells in an electrically erasable and programmable device of the type having a plurality of cells each comprising a single transistor having a source, a drain, a control gate, and a floating gate positioned between the control gate and the source and drain, and further of the type having a plurality of row address lines each coupled to the control gates of the cells in an associated row, a plurality of column address lines each coupled to the drains of the cells in an associated column, and a plurality of source lines coupled to the sources of the cells, the method comprising the steps of: (a) separately testing each column for the presence of over-erased cells; and (b) individually testing the cells in columns found to have over-erased cells to determine which cells are over-erased, including the steps of (i) selecting a cell to be tested, and (ii) raising the sources of all cells within said column to a potential which biases cells in said column, which cells are over-erased but are not selected, into a non-conducting state, (iii) placing the selected cell in a predetermined electrical condition, which includes the steps of (1) applying a voltage of approximately 1.2 volts to the column address line associated with the cell, (2) applying a voltage of approximately 0.6 volts to the source line associated with the cell, and (3) applying voltages in a range of approximately 0 volts to approximately 2.0 volts to the row address line associated with the cell; (iv) reading the selected cell in a read operation; and (v) determining whether current is flowing into the selected cell which, when a cell is in the predetermined electrical. Condition, is an indication that it is over-erased.

Claim 9

A method of identifying over-erased cells in an electrically erasable and programmable device of the type having a plurality of cells each comprising a single transistor having a source, a drain, a control gate, and a floating gate positioned between the control gate and the source and drain and wherein Fowler-Nordheim tunneling is used for tunneling electrons from the source to the floating gate and for tunneling electrons from the floating gate to the drain and further of the type having a plurality of row address lines each coupled to the control gates of the cells in an associated row, a plurality of column address lines each coupled to the drains of the cells in an associated column, and a plurality of source lines coupled to the sources of the cells, the method comprising the steps of: (a) simultaneously testing all cells in the device for the presence of over-erased cells; and (b) individually testing the cells if the device is found to have over-erased cells to determine which cells are over-erased.

Claim 10

A method of identifying over-erased cells in an electrically erasable and programmable device of the type having a plurality of cells each comprising a single transistor having a source, a drain, a control gate, and a floating gate positioned between the control gate and the source and drain and wherein Fowler-Nordheim tunneling is used for tunneling electrons from the source to the floating gate and for tunneling electrons from the floating gate to the drain and further of the type having a plurality of row address lines each coupled to the control gates of the cells in an associated row, a plurality of column address lines each coupled to the drains of the cells in an associated column, and a plurality of source lines coupled to the sources of the cells, the method comprising the steps of: (a) simultaneously testing all cells in the device for the presence of over-erased cells; and (b) individually testing the cells if the device is found to have over-erased cells to determine which cells are over-erased.

Claim 12

A method of identifying over-erased cells in an electrically erasable and programmable device of the type having a plurality of cells each comprising a single transistor having a source, a drain, a control gate, and a floating gate positioned between the control gate and the source and drain and wherein Fowler-Nordheim tunneling is used for tunneling electrons from the source to the floating gate and for tunneling electrons from the floating gate to the drain and further of the type having a plurality of row address lines each coupled to the control gates of the cells in an associated row, a plurality of column address lines each coupled to the drains of the cells in an associated column, and a plurality of source lines coupled to the sources of the cells, the method comprising the steps of: (a) simultaneously testing all cells in the device for the presence of over-erased cells, including the steps of (i) placing the cells in the device in a predetermined electrical condition which includes the steps of (1) applying a voltage of approximately 1.2 volts to the column address lines associated with each column, (2) applying a voltage of approximately 0.6 volts to the source lines associated with the cells in each column, and (3) applying a voltages in a range of approximately 0 volts to approximately 2.0 volts to the row address lines associated with the cells in each column; (ii) reading the cells in a simultaneous read operation; and (iii) determining whether current is flowing into the cells which, when the cells are in the predetermined electrical condition, is an indication that over-erased cells are present in the device; and (b) individually testing the cells if the device is found to have over-erased cells to determine which cells are over-erased.

Claim 13

A method of identifying over-erased cells in an electrically erasable and programmable device of the type having a plurality of cells each comprising a single transistor having a source, a drain, a control gate, and a floating gate positioned between the control gate and the source and drain and wherein Fowler-Nordheim tunneling is used for tunneling electrons from the source to the floating gate and for tunneling electrons from the floating gate to the drain and further of the type having a plurality of row address lines each coupled to the control gates of the cells in an associated row, a plurality of column address lines each coupled to the drains of the cells in an associated column, and a plurality of source lines coupled to the sources of the cells, the method comprising the steps of: (a) simultaneously testing all cells in the device for the presence of over-erased cells, including the steps of (i) placing the cells in the device in a predetermined electrical condition which includes the steps of (1) applying a voltage of approximately 1.2 volts to the column address lines associated with each column, (2) applying a voltage of approximately 0.6 volts to the source lines associated with the cells in each column, and (3) applying a voltages in a range of approximately 0 volts to approximately 2.0 volts to the row address lines associated with the cells in each column; (ii) reading the cells in a simultaneous read operation; and (iii) determining whether current is flowing into the cells which, when the cells are in the predetermined electrical condition, is an indication that over-erased cells are present in the device; and (b) individually testing the cells if the device is found to have over-erased cells to determine which cells are over-erased.

Claim 15

A method of identifying over-erased cells in an electrically erasable and programmable device of the type having a plurality of cells each comprising a single transistor having a source, a drain, a control gate, and a floating gate positioned between the control gate and the source and drain and wherein Fowler-Nordheim tunneling is used for tunneling electrons from the source to the floating gate and for tunneling electrons from the floating gate to the drain and further of the type having a plurality of row address lines each coupled to the control gates of the cells in an associated row, a plurality of column address lines each coupled to the drains of the cells in an associated column, and a plurality of source lines coupled to the sources of the cells, the method comprising the steps of: (a) simultaneously testing all cells in the device for the presence of over-erased cells; and (b) individually testing the cells if the device is found to have over-erased cells to determine which cells are over-erased, including the steps of (i) placing each of the cells in a predetermined electrical condition, which includes the steps of (1) applying a voltage of approximately 1.2 volts to the column address line associated with the cell, (2) applying a voltage of approximately 0.6 volts to the source line associated with the cell, and (3) applying a voltage in a range of approximately 0 volts to approximately 2.0 volts to the row address line associated with the cell; (ii) reading each of the cells in a read operation; and (iii) determining whether current is flowing into each of the cells which, when a cell is in the predetermined electrical condition, is an indication that it is over-erased.

Claim 16

A method of identifying over-erased cells in an electrically erasable and programmable device of the type having a plurality of cells each comprising a single transistor having a source, a drain, a control gate, and a floating gate positioned between the control gate and the source and drain and wherein Fowler-Nordheim tunneling is used for tunneling electrons from the source to the floating gate and for tunneling electrons from the floating gate to the drain and further of the type having a plurality of row address lines each coupled to the control gates of the cells in an associated row, a plurality of column address lines each coupled to the drains of the cells in an associated column, and a plurality of source lines coupled to the sources of the cells, the method comprising the steps of: (a) simultaneously testing all cells in the device for the presence of over-erased cells; and (b) individually testing the cells if the device is found to have over-erased cells to determine which cells are over-erased, including the steps of (i) placing each of the cells in a predetermined electrical condition, which includes the steps of (1) applying a voltage of approximately 1.2 volts to the column address line associated with the cell, (2) applying a voltage of approximately 0.6 volts to the source line associated with the cell, and (3) applying a voltage in a range of approximately 0 volts to approximately 2.0 volts to the row address line associated with the cell; (ii) reading each of the cells in a read operation; and (iii) determining whether current is flowing into each of the cells which, when a cell is in the predetermined electrical condition, is an indication that it is over-erased.

Claim 17

A method of identifying over-erased cells in an electrically erasable and programmable device of the type having a plurality of cells each comprising a single transistor having a source, a drain, a control gate, and a floating gate positioned between the control gate and the source and drain, and further of the type having a plurality of row address lines each coupled to the control gates of the cells in an associated row, a plurality of column address lines each coupled to the drains of the cells in an associated column, and a plurality of source lines coupled to the sources of the cells, the method comprising the steps of: (a) separately testing groups of cells for the presence of over-erased cells within each group; and (b) individually testing the cells in groups found to have over-erased cells to determine which cells are over-erased, including the steps of (i) selecting a cell to be tested and (ii) raising the sources of all cells within said column to a potential which biases cells in said column, which cells are over-erased but are not selected, into a non-conducting state.

Claim 18

A method of identifying over-erased cells in an electrically erasable and programmable device of the type having a plurality of cells each comprising a single transistor having a source, a drain, a control gate, and a floating gate positioned between the control gate and the source and drain, and further of the type having a plurality of row address lines each coupled to the control gates of the cells in an associated row, a plurality of column address lines each coupled to the drains of the cells in an associated column, and a plurality of source lines coupled to the sources of the cells, the method comprising the steps of: (a) separately testing groups of cells for the presence of over-erased cells within each group; and (b) individually testing the cells in groups found to have over-erased cells to determine which cells are over-erased, including the steps of (i) selecting a cell to be tested and (ii) raising the sources of all cells within said column to a potential which biases cells in said column, which cells are over-erased but are not selected, into a non-conducting state.